Why does the Avalon-ST dual-clock FIFO not transmit the data at the output?

[AFrei11]

I'm quiet new to FPGA programming and I'm trying to implement the Avalon-ST dual-clock FIFO in my application. As you can see in the picture the FIFO accepts Input Data until the FIFO depth of 16 is reached. The Output on the other hand doesn't send the Data out as you can see by the valid signal not changing.

Has anyone ever dealt with such a problem?

Regards

[sstrell]

It looks like out_reset_n is being held low, which would be holding the output in reset.

#iwork4intel

[AFrei11]

Thank you very much for your answer

I have not connected the two resets to the same source.

Now the FIFO is working.

Thank you for your help