I am working on SEN02G64C4BH2MT-30WR DDR2. i am using uniphy ip in quartus. (Stratix 4)
I am able to do single write and read to a particular address location with specific data.
For bulk data read and write, i incremented address location and data by one, in top vhdl file (avl_addr = avl_addr +1 and avl_wdata = avl_wdata + 1). but am i missing some of data.
pll_ref_clk = 100MHz.
afi_clk = 266.66 MHz
MEM_CLK = 133.33Mhz (half rate).
Remember that with Avalon in Platform Designer, masters, by default, use byte addressing while slaves, like the memory IP, use word addressing. You don't mention what your data width is, but if, for example, it's 32 bits, you need to increment the address by 4 on the master to get to the next 32-bit data.
Another thing to watch out is the DDR2 IP local_be signal, byte enable signal setting.
Feel free to try and error to increment the avl_addr as it's unclear which path in your design is facing the issue now
One thing to take note is you can add signal_tap to monitor your avalon bus transaction to see where thing goes wrong to figure out the issue is with your avalon master or any QSYS interconnect bridge or on your DDR2 IP avalon slave side