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rsing108
New Contributor I
749 Views

can't program stratix 10 GX with pcie hard ip+ example design

I am getting the following errors while programming the Stratix 10 GX board with the PCIE hard ip+ example design.

quartus_pro 19.4

Error (18950): Device has stopped receiving configuration data
Error (18948): Error message received from device: Detected hardware access error. There is a failure in accessing external hardware. (Subcode 0x0032, Info 0x00000000, Location 0x0000CC00)
Error (20072): A PMBUS error has occurred during configuration. Potential errors: Incorrect VID setting in Quartus Project. The target device fails to communicate to smart regulator or PMBUS Master on board.

Why am I getting these errors as all vid settings are auto generated? How to solve these issues?

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19 Replies
SengKok_L_Intel
Moderator
743 Views

Hi,


To better understanding the problem, could you please provide the following info?


  1. How do you generate the example design? Is this from the IP GUI?
  2. Did you connect the board to a proper setup, where there is PCIe reference clock coming to the FPGA end point?


Regards -SK


rsing108
New Contributor I
741 Views

Hi @SengKok_L_Intel ,

I generated this example design using Quartus pro GUI. Specifically, I am following the steps present here 

https://www.intel.com/content/www/us/en/programmable/documentation/sox1520633403002.html#zjk15206332...

SengKok_L_Intel
Moderator
738 Views

Thanks for the reply.


Did you connect the PCIe End point to the root port with the proper PCIe reference clock before you program the SOF? If without a proper PCIe reference clock, you will fail the programming.


Regards -SK


rsing108
New Contributor I
735 Views

Hi @SengKok_L_Intel ,

I did not find any such step in the manual so I have not specifically defined it, but shouldn't it be already done while generating the example design? Also does this attachment help or should I provide any other file? Sorry, I am not much familiar with this IP.

rsing108_0-1600915361139.png

 

SengKok_L_Intel
Moderator
729 Views

What I mean is, do you physically connect the development kit (Endpoint) with a Host PC (Rootport) when you program the FPGA?


rsing108
New Contributor I
727 Views

Hi @SengKok_L_Intel 

The refclk pin is connected to PIN_AK41

I am attaching the .qsf file for all the pin assignments and while generating the design I parameterized the port type as "native endpoint" and not "Root port".

SengKok_L_Intel
Moderator
726 Views

Hi,


I believe you are using this development kit?

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s1...


Do you actually slot this card into a host PC?


Regards -SK


rsing108
New Contributor I
725 Views

Yes the device ID is 1SG280LN2F43E2VG and is placed in a server along with another exactly same card

SengKok_L_Intel
Moderator
718 Views

Hi,


Are you using a custom board and this is not Intel FPGA development kit? I'm asking this is because, the device ID 1SG280LN2F43E2VG is not the same as Stratix 10 Development Kit at the link below:  


https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s1...


Other questions:

  1. Does the server is power up, and there is a valid PCIe clock sending from the server to FPGA when you program the FPGA?
  2. Do you able to program a simple design (without the PCIe)?


Regards -SK




rsing108
New Contributor I
715 Views

Hi @SengKok_L_Intel ,

It's actually BittWare's 520n card:

https://www.bittware.com/fpga/520n/

There is a valid PCIE clock being sent to the FPGA and I am able to program a simpler design without PCIE ip

SengKok_L_Intel
Moderator
710 Views

Hi,


Can you send me your simple design 's QSF file that able to program successfully? I would like to have a look of the Power setting and see if there is any difference.


Regards -SK


rsing108
New Contributor I
707 Views

I am attaching the qsf file of my simple design and I am also attaching the qsf of a vendor provided design which also has pcie instantiated 

SengKok_L_Intel
Moderator
701 Views

As i can see, you did not change the power and VID settings accordingly. Could you please give it a try of the attached qsf file?

 

Regards -SK

rsing108
New Contributor I
697 Views

Hi @SengKok_L_Intel ,

The previous errors are gone but now I am getting this error:

Error (18950): Device has stopped receiving configuration data
Error (18948): Error message received from device: Device is in configuration state.
Error (209012): Operation failed

Tags (1)
SengKok_L_Intel
Moderator
694 Views

From the vendor.qsf file, the PCIe reference clock is using T34, but you are using AK41. Could you please double check? Or perhaps you can get a simple PCIe design from Bittware?


set_location_assignment PIN_T34 -to pcie_refclk


Regards -SK


rsing108
New Contributor I
690 Views

Hi @SengKok_L_Intel ,

I changed the refclk pin to the same as the vendor one and also changed the rest of the pins according the vendor's pin configuration. But there is still an error while programming the board:

Error(18952): Error status: Device does not accept configuration request

rsing108
New Contributor I
687 Views

Hi @SengKok_L_Intel ,It seems I need to get the server rebooted first. I will update you once I get it rebooted. 

SengKok_L_Intel
Moderator
668 Views

Thank for the update. If this still can't work, probably you can request a simple design from Bittware that can work properly for reference. This is to ensure all the pin assignments and VID setting are correct.


Regards -SK


SengKok_L_Intel
Moderator
650 Views

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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