Constraining output clocks properly in *.SDC

[Erica]

Hi,

I am generating a clock with a PLL that will also be driving an external device. I am using a clock buffer (altclkctrl) in between and wondering how to constrain it properly? I'm currently using the following in my *.sdc:

create_generated_clock -name {CLK_OUT} -source [get_pins {pll_inst|altpll_component|auto_generated|pll1|clk[0]}] -multiply_by 1 -divide_by 1 [get_ports {SDRAM_OUT}]

I noticed on another post that when the "altclkctrl" is used to drive the global clock network, that it doesn't need to be constrained as it is just wires. Is it the same when the "altclkctrl" is used as an output clock buffer?

I am also detecting "Minimum Pulse Width" violations since I added the output clock buffer.

Thank you very much,

Erica

[sstrell]

All clocks need to be constrained, no matter what resources are used.  Your constraint for the output clock is correct.  Add this

set_false_path -to [get_ports {SDRAM_OUT}]

so that the output clock path is not analyzed as a data path.

[Erica]

Okay perfect!

Thank you very much again,

Erica

[Erica]

Hi again,

I just realized I had made a type (SDRAM_OUT was supposed to also be named CLK_OUT). Anyway, I'm wondering why I'm still getting a min pulse width violation? I was wondering if you had any idea?

Thanks again,

Erica

[sstrell]

You'd need to check to see if the target device's PLL you are using is capable of whatever clock speed you are trying to generate.  Perhaps it's too fast, causing the violation.

[Erica · Accepted solution]

Okay that makes sense. For now I'm using an eval board and this clock is not on a designated clock pin. When I compile it gives me a warning under Fmax "limit due to minimum port rate restriction"  that it can only achieve up to 125MHz and we are running above that. In the final version, this pin will be routed on an actual clock pin.