Data from FPGA to host

[Altera_Forum]

Hi, 

I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read this (http://www.alteraforum.com/forum/showthread.php?t=32354) and there's instructive information but it's a bit old and maybe there exist other ways. I thought about a FIFO that would be written by the FPGA then read by the host through the USB link. Is it possible? Have I to use a virtual JTAG component? Thanks for your help.

[Altera_Forum]

--- Quote Start ---  has the JTAG to Avalon master bridge you use to be implemented?    --- Quote End ---   Its a standard Qsys component.    --- Quote Start ---   The signals from the fifo have to go to the sdram controller or to the cpu?   --- Quote End ---   That is up to you.    --- Quote Start ---   The commands you use (as jtag_read or jtag_write) can be used by the cpu or only in the console?  --- Quote End ---   The NIOS II CPU cannot "see" the JTAG port, since it is inside the FPGA. You need to use System Console from the host. If all you need is something to generate an Avalon-MM read or write, then you can use the NIOS II processor to generate the transaction. If your SignalTap II trace is at the Avalon-MM slave interface, then either the CPU or JTAG-to-Avalon-MM master can be used.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  That is up to you.  --- Quote End ---   OK but I really don't know what difference it makes. What have I to do in one case or the other?    --- Quote Start ---  If all you need is something to generate an Avalon-MM read or write, then you can use the NIOS II processor to generate the transaction. If your SignalTap II trace is at the Avalon-MM slave interface, then either the CPU or JTAG-to-Avalon-MM master can be used.  --- Quote End ---   I still can't understand what need the SignalTap II trace is. Here's what I tried first: Download the design in the FPGA. This design was waiting an activity on any observed input signal to start the recording in the "onchip memory" (so told qsys). This memory is too small to capture the whole process so I thought of using the sdram.  I thought of using this procedure: 1. download the design in the FPGA 2. start a waiting command in the console 3. start the observed process and record the signals in the sdram 4. detecting the end of the process and then write the content of the sdram in a file on the host computer  Does this way of doing it seem to be OK?

[Altera_Forum]

--- Quote Start ---   I still can't understand what need the SignalTap II trace is.   --- Quote End ---   Its a debug tool. Read the documentation. Try and use it. Once you understand how to use it, you will be able to determine if its useful to you.    --- Quote Start ---   Here's what I tried first: Download the design in the FPGA. This design was waiting an activity on any observed input signal to start the recording in the "onchip memory" (so told qsys). This memory is too small to capture the whole process so I thought of using the sdram.   --- Quote End ---   Unfortunately SignalTap II cannot use external memory. Typically you do not need to record "all" of a transaction though, you can use Triggers to capture relevant details.    --- Quote Start ---   I thought of using this procedure: 1. download the design in the FPGA 2. start a waiting command in the console 3. start the observed process and record the signals in the sdram 4. detecting the end of the process and then write the content of the sdram in a file on the host computer  Does this way of doing it seem to be OK?  --- Quote End ---    Sure, if you can define what a "waiting command" is in your hardware design.  Have you created a simulation of your system? If not, you should. It will help you understand your design much better, since it gives you full visibility into what is going on. The simulation waveform view will also help you see why SignalTap II is useful.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Its a debug tool. Read the documentation. Try and use it. Once you understand how to use it, you will be able to determine if its useful to you.  --- Quote End ---   I used it some time ago and I know basically what it can do. I don't know it very well and I can be wrong but I don't think it could be very useful for the matter.    --- Quote Start ---   Sure, if you can define what a "waiting command" is in your hardware design.  --- Quote End ---   I was thinking of a flag that would only make the sdram writing enable when it's '1'.    --- Quote Start ---  Have you created a simulation of your system? If not, you should. It will help you understand your design much better, since it gives you full visibility into what is going on. The simulation waveform view will also help you see why SignalTap II is useful.  --- Quote End ---   You're right, I haven't done so and I'm starting to think it's a big error. I'll do it first thing tomorrow (if my work let me enough time)...

[Altera_Forum]

And here is another problem: I tried http://www.alterawiki.com/wiki/simulating_designs_with_lower-level_qsys_systems#setting_up_and_generating_the_simulation_environment_in_qsys and it told me to do http://www.altera.com/support/examples/nios2/exm-simulating-niosii.html but things are not as it should be. In Modelsim I don't see the same signals as in the tutorial. Maybe it's a difference in the versions (6.6d in the tutorial and I'm using 10.1d) or maybe I'm not doing what is needed. I'll investigate this tomorrow...

[Altera_Forum]

I don't know why but I can't post the links. I tried tutorials but it doesn't run as wanted, maybe a version difference or maybe it's my fault. I'll try another time tomorrow...

[Altera_Forum]

--- Quote Start ---  I tried tutorials but it doesn't run as wanted, maybe a version difference or maybe it's my fault. I'll try another time tomorrow...  --- Quote End ---   SignalTap II? I use it all the time with various version of the tools and have never had a problem.  Synthesize your design, then start SignalTap II, add signals to the SignalTap II instance, setup a clock source, setup the number of samples to capture, save the instance, add it to your project, resynthesize, download to your board, and then 'scan JTAG chain' in SignalTap II (if it doesn't auto detect that the instance is now valid).  Cheers, Dave

[Altera_Forum]

OK, I didn't understand you correctly 

For me "simulation" means a logical way of predicting what would happen, with Modelsim or Questa for example. SignalTap II is more a tool to analyse what really happens after downloading the design in the FPGA. Anyway it's more what I need. I used it some time ago but my knowledge (and my memory) seems to need an update. That's what I'll do next and see if it helps...

[Altera_Forum]

--- Quote Start ---   For me "simulation" means a logical way of predicting what would happen, with Modelsim or Questa for example. SignalTap II is more a tool to analyse what really happens after downloading the design in the FPGA.   --- Quote End ---   In general, you have to use both. For example, lets say I have a board with a microcontroller on it, and the firmware in that microcontroller implements a parallel interface to the FPGA, and I do not have access to that firmware (eg., I have this situation on a Digilent Xilinx board). Using SignalTap II (or in reality Xilinx Chipscope), I can measure the timing of that interface, and then use that timing in the bus functional model (BFM) simulation of the parallel interface. Once I have a realistic BFM, I can simulate the design until I am confident it works, and then hardware test. Working this way, I generally have no issues once I get to hardware tests.  Cheers, Dave

[Altera_Forum]

OK, I still have simulation problems but I know why (I think). I'll repair that and continue... 

Tell me something I don't know: what need are the constraints? I see that Quartus II is complaining when I don't do that part but why? For me, doing things without any constraint is easier but it wants to be constrained!

[Altera_Forum]

--- Quote Start ---   Tell me something I don't know: what need are the constraints? I see that Quartus II is complaining when I don't do that part but why? For me, doing things without any constraint is easier but it wants to be constrained!  --- Quote End ---   An FPGA design typically requires; HDL code to describe the design, FPGA device and device settings (eg, what to do with unused pins), pinout constraints, and timing constraints.  The first two things are absolutely required. The timing constraints are not required to synthesize a design, but Quartus will complain, because it recognizes that you are using synchronous logic (clocks), but it has no idea how what clock frequency you expect your design to operate at. That is why you have to provide timing constraints.  Cheers, Dave

[Altera_Forum]

Here is my problem of the day: 

I'm using SignalTap II with three signal. The first one is acting as the clock and the others are represented on this image: https://www.alteraforum.com/forum/attachment.php?attachmentid=10256  ext_s0 is acting as the trigger on either edge so I would think it's constant before 0 but it's not. Can you explain?

[Altera_Forum]

--- Quote Start ---   ext_s0 is acting as the trigger on either edge so I would think it's constant before 0 but it's not. Can you explain?  --- Quote End ---   Have you ever used an oscilloscope? When you trigger on a clock-like signal, the edge that the oscilloscope triggers on is not the "first edge" of the clock it is "an edge". The same is happening in your SignalTap II trace. When you arm the trigger, it captures the first edge after the arm command ...   Cheers, Dave

[Altera_Forum]

OK for your explanation. 

I was hoping the data to be recorded in a file I could get and give to my host program but I need the whole process so it doesn't seem a good idea...

[Altera_Forum]

I tried to begin the process 15 minutes after the start of the acquisition. This way I was pretty sure the trigger was armed and the first edge would be captured but it's not, I can still see activity before 0. 

Now SignalTap II is giving a trace, what should I do to write all the process in the sdram (it's the finality I want to obtain)?

[Altera_Forum]

--- Quote Start ---   what should I do to write all the process in the sdram (it's the finality I want to obtain)?   --- Quote End ---   Its a bit difficult to comment on this, as I don't really understand what you are trying to do.  As I commented earlier, you should be using simulation to test your design, and use SignalTap II to determine real-world stimulus for your simulation.  If you have not created a simulation of your system, you're making your life more difficult than it needs to be.  Create a simulation, create stimulus, and then try to make the simulation match your real world signals.  Cheers, Dave

[Altera_Forum]

As I said, an external design is computing 4 signals, they are inputs on my de0-nano's GPIOs and one of them is acting as an external clock. I want to record all what happens during a certain process. I want this process to be analysed by a program (a C one) on the host computer. 

I made a design that could record it in the SRAM but this memory was not large enough so I thought of writing in the SDRAM and that's where I'm stuck because I don't know how to work it. For a real simulation I would have to know how to simulate a Qsys design and the program running on the Nios but it seems complicated for me. I've done the SignalTap part but it doesn't seem useful if I can't simulate my design, right?

[Altera_Forum]

--- Quote Start ---  As I said, an external design is computing 4 signals, they are inputs on my de0-nano's GPIOs and one of them is acting as an external clock.   --- Quote End ---   Ok. This sounds pretty simple. I'm not sure why you cannot trigger SignalTap II correctly then. I've had plenty of setups where I want to capture the "first" transition on a signal and it worked fine, eg., even at power-on using the power-on trigger feature within SignalTap II.    --- Quote Start ---   I want to record all what happens during a certain process. I want this process to be analysed by a program (a C one) on the host computer. I made a design that could record it in the SRAM but this memory was not large enough so I thought of writing in the SDRAM and that's where I'm stuck because I don't know how to work it. For a real simulation I would have to know how to simulate a Qsys design and the program running on the Nios but it seems complicated for me. I've done the SignalTap part but it doesn't seem useful if I can't simulate my design, right?  --- Quote End ---    Everything is complicated until you've figured out how to do it :)  Did you simulate your simpler SRAM design? You should be able to simulate data capture into SRAM, then synthesize it, and check that it works ok in hardware. Once you've convinced yourself that works, you could go onto using the SDRAM for longer data capture, and then skip simulating that more complicated system if you think you need to.  Personally, I simulate everything until I understand what needs to happen, and then the hardware "just works".   How did I learn to use the simulator? I spent time learning how to use it. You'll need to do the same.  Cheers, Dave

[Altera_Forum]

I think I don't have to use a Nios cpu. I prefer to use a system like the one in your de0_nano_sdram tutorial. Only I have to add PIOs to read from/write to my fifo in the Quartus top-level. I just have to add commands in the jtag_cmds.tcl script to access these PIOs. Is it possible the way you wrote it? 

 For the simulation, I think (after wondering and having problems without that) it's really important. I PROMISE I will learn how to do it but I don't find a good tutorial for that. I've found Simulating Designs with Lower-Level Qsys Systems or AN351 but it's with a Nios II and I'd like a simpler tutorial with a simpler Qsys system but I don't find any for now. Do you know any? Or maybe you even wrote one.

[Altera_Forum]

--- Quote Start ---  I think I don't have to use a Nios cpu. I prefer to use a system like the one in your de0_nano_sdram tutorial. Only I have to add PIOs to read from/write to my fifo in the Quartus top-level. I just have to add commands in the jtag_cmds.tcl script to access these PIOs. Is it possible the way you wrote it?   --- Quote End ---   That will depends on what the PIOs are doing. If they are static, then sure you can just read them. In your earlier posts, you commented you wanted to read toggling signals. In that case, you really need to capture them first, eg., into on-chip RAM, or into SDRAM, and then read them out via JTAG. This is pretty much what SignalTap II does (with the samples stored in on-chip RAM). If you cannot figure out how to trigger SignalTap II correctly, then you'll probably having trouble getting this scheme to work too.    --- Quote Start ---   For the simulation, I think (after wondering and having problems without that) it's really important. I PROMISE I will learn how to do it but I don't find a good tutorial for that. I've found Simulating Designs with Lower-Level Qsys Systems or AN351 but it's with a Nios II and I'd like a simpler tutorial with a simpler Qsys system but I don't find any for now. Do you know any? Or maybe you even wrote one.  --- Quote End ---   I gave you a link to a tutorial back in Post#35.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  That will depends on what the PIOs are doing. If they are static, then sure you can just read them. In your earlier posts, you commented you wanted to read toggling signals. In that case, you really need to capture them first, eg., into on-chip RAM, or into SDRAM, and then read them out via JTAG. This is pretty much what SignalTap II does (with the samples stored in on-chip RAM). If you cannot figure out how to trigger SignalTap II correctly, then you'll probably having trouble getting this scheme to work too.  --- Quote End ---   I'm not English so I think I miss some subtlety in the words and I'm not sure I understand it correctly: the signals are coming from a fifo. Is it correct to say they're static? Or how can I manage it?     --- Quote Start ---   I gave you a link to a tutorial back in Post#35.   --- Quote End ---   I should have read it too quickly, I'll read it again and more carefully...