FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits

Nios to FPGA Avalon-MM

aamodini
Neuer Beitragender I
1.709Aufrufe

I want to transfer data from Nios (host) to a custom agent component on the FPGA through Avalon-MM interface. But, the host and agent operate at different clock speeds. How to facilitate data transfer in this scenario?

Beschriftungen (2)
0 Kudos
9 Antworten
sstrell
Geehrter Beitragender III
1.679Aufrufe

In Platform Designer, just connect them together.  The generated interconnect will automatically include CDC logic, either a FIFO or handshaking, depending on the options you set in PD (I think it's Interconnect Requirements in Standard and the Domains tab in Pro).

If you want more control, you can manually add/insert an Avalon clock crossing bridge from the IP Catalog.

aamodini
Neuer Beitragender I
1.641Aufrufe

I am trying to use the Avalon-MM Clock Crossing Bridge, but am confused regarding a few connections on PD.

aamodini_0-1723737606341.png

m0_clk and m0_reset are connected to the Nios processor clk and reset respectively (125 MHz) and s0_clk is connected to the clock bridge at 100 MHz. avalon_slave_0 is my custom Avalon-MM slave component. How should s0 and m0 interfaces be connected, if Nios is the host and avalon_slave_0 is the agent?

sstrell
Geehrter Beitragender III
1.617Aufrufe
aamodini
Neuer Beitragender I
1.566Aufrufe

Thank you.

I get the following error when I connect m0 to custom component

Error: system.mm_ccb_0.m0: avalon_slave_0.avalon_slave_0 (0x41160..0x4116f) is outside the master's address range (0x0..0x3f)

I have assigned base addresses to all the components.

aamodini_0-1723830524919.pngaamodini_1-1723830536941.png

 

sstrell
Geehrter Beitragender III
1.564Aufrufe

You set the address width to only 4 bits for the bridge and you're using an address much larger than that.  Just turn on "Use automatically determined address width."

aamodini
Neuer Beitragender I
1.551Aufrufe

I get other errors when I turn on "Use automatically-determined address width"

aamodini_0-1723832891531.png

 

sstrell
Geehrter Beitragender III
1.534Aufrufe

As it says, the address spaces are overlapping.  Either manually adjust them or auto-assign base addresses again.

I'd recommend checking out the user guide for how to set up memory-mapped addressing: https://www.intel.com/content/www/us/en/docs/programmable/683609/24-2/64-bit-addressing-support.html

JingyangTeh_Altera
Mitarbeiter
975Aufrufe

Hi aamodini


Do you have any follow up question regarding this issue?


Regards

Jingyang, Teh


JingyangTeh_Altera
Mitarbeiter
934Aufrufe

Hi


As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Regards

Jingyang, Teh


Antworten