OpenCL 19.3 SD Card image for Intel Arria 10 Development Kit

[CJohn56]

Hi,

I am having problems with creating my own SD Card image for the Intel Arria 10 Development Kit.

I have tried the GSRD 19.1, but I cannot get the OpenCL Driver working.

I have also tried generating the device tree blob, compiling Linux, compiling u-boot, compiling the OpenCL driver approach, without luck.

Is there a pre compiled OpenCL driver or precompiled SD Card image for 19.1/19.3? I've noticed that there is an image in the 17.1 SDK, and there should be one for the 18.1 SDK (https://forums.intel.com/s/question/0D50P00004KyuxESAR/getting-started-with-the-intel-fpga-sdk-for-opencl-pro-edition-for-linux), but I can't seem to find one for 19.1.

[MEIYAN_L_Intel]

Hi,

As of version 19.1, Intel no longer ship the SD card image for the SoC. This is due to Intel licensing policies and Linux.

I had found that the document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/ug-aocl-a10socdk-platform.pdf,

is provided instructions on how to how to create your own SD card image in Chapter 3.

Can you tried the instructions as stated in the document?

Thanks

[CJohn56]

Hi Mylee,

Ok, thanks for the update.

Regarding step 1. in 3.1, what is meant by "Run base revision compile (aoc -bsp-flow=base) with your a10socdevelopment kit BSP in the following location: $INTELFPGAOCLSDKROOT/board/a10soc" ?

When I run it in the stated folder, I get "Error: No input file detected". I don't see any .cl files in that folder or sub folders. Should I run it on "$INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/boardtest.cl" as stated in 2.3?

[MEIYAN_L_Intel]

Hi,

According to the document: "You must compile the device tree blob contained in the FAT partition to match your Intel Arria 10 SoC Development Kit Reference Platform. Use the Device Tree Generator (sopc2dts) and the Device Tree Compiler (dtc) to generate the necessary device tree blob. "

May I know do you have generate the device tree blob?

Thanks

[CJohn56]

Hi,

No, that is what I'm having problems with: step 1 in section "3.1. Compiling the Device Tree Blob" states that I must "Run base revision compile (aoc -bsp-flow=base) with your a10socdevelopment kit BSP in the following location: $INTELFPGAOCLSDKROOT/board/a10soc". However, the aoc command is for compiling .cl files, and there aren't any .cl files in $INTELFPGAOCLSDKROOT/board/a10soc or in the subfolders.

[MEIYAN_L_Intel]

Hi,

As mentioned "what is meant by "Run base revision compile (aoc -bsp-flow=base) with your a10socdevelopment kit BSP in the following location: $INTELFPGAOCLSDKROOT/board/a10soc'", this is used when porting the a10soc Reference Platform to your own Custom Platform. The Intel Quartus Prime Pro Edition software compiles this base project revision from source code. 

For the problem regarding, I would like to have some time to looking into it.

Thanks

[MEIYAN_L_Intel]

Hi,

You may need to have a own kernel file (.cl file) in order to perform the base revision compiles compile as i seen in the document stated: "To compile to base revision, add the -bsp-flow=base argument to aoc command (for example, aoc -bsp-flow=base myKernel.cl). "

Thanks

[CJohn56]

Hi,

I have tried running

aoc -bsp-flow=base vector_add.cl

on the vector_add example project. During step 3.2.3, I get a lot of "component _ is unknown" and "DTAppend: Unable to find parent, null, for _. Adding to root". Is this to be expected? I have attached the output from running the sopc2dts command.

I have tried with both the board.qsys file that comes with the SDK, in $INTELFPGAOCLSDKROOT/board/a10soc/hardware/a10soc_2ddr/, the board.qsys that comes with the base revision compile and the one from the downloadable BSP.

I think it might relate to:

"Ensure that the name of the Intel Arria 10 Hard Processor System inyour board.qsys file matches the name used in Intel Arria 10 GHRDproject you are downloading the XML files from. At the time thisdocument was written, the name of the Intel Arria 10 Hard ProcessorSystem in board.qsys and in Intel Arria 10 GHRD project wasa10_hps.Create your copy of the Intel Arria 10 SoC BSP from the SDK, andrename the instance of the Intel Arria 10 Hard Processor System inboard.qsys to a10_hps."

As stated in part three of section 3.1 in the guide. But I am not sure where and in what files it should say one or the other.

[MEIYAN_L_Intel]

Hi,

You have to open .qsys to see the name of the component whether the name of components is match with .xml file. 

For an example according to https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/fb127751.html,

there is an unknown in hps_0, which mean the name of the component in .qsys file and .xml file is not match. 

You have to rename it, so that the name in .qsys file and .xml file is match. 

Thanks

[CJohn56]

Hi,

I couldn't manage to get it working by editing the .qsys file directly, as I am not sure of the structure of the .qsys file. In other words, I wasn't sure which fields I should and should not edit. However, I tried to open the .qsys in the "Platform Designer". Here, it complained about all of the IPs being version 17.1, when my version of the entire toolchain is version 19.3. After that, it upgraded all of the IPs and I changed the name of the Hard Processor. After that, I was able to run sopc2dts without getting any "DTAppend" errors. However, there is still a lot of unknown components, as can be seen in the attached file "sopc2dts_output.txt".

Then I edited the .dts file as stated by the manual, and ran the dtc command. This command produced the following errors:

ERROR (phandle_references): Reference to non-existent node or label "led_pio"   ERROR (phandle_references): Reference to non-existent node or label "led_pio"   ERROR (phandle_references): Reference to non-existent node or label "led_pio"   ERROR (phandle_references): Reference to non-existent node or label "led_pio"   Warning: Input tree has errors, output forced

Even though the steps in section "3.4 Generating Full-Chip Programming File for SD Card Image" runs without any problems, should these error messages be here?

Then I tried to compile the OpenCL driver against ACDS19.1 version of linux_socfpga. Even after the fix made in "aclsoc_cmd.c", as stated in the manual, I get the following error:

CC [M] /home/carljohnsen/git/a10soc_driver/aclsoc_cmd.o /home/carljohnsen/git/a10soc_driver/aclsoc_cmd.c: In function ‘__aclsoc_get_user_pages’: /home/carljohnsen/git/a10soc_driver/aclsoc_cmd.c:166:11: error: too few arguments to function ‘get_user_pages_remote’ ret = get_user_pages_remote(target_task, target_task->mm, ^~~~~~~~~~~~~~~~~~~~~

This can be fixed by giving it an additional pointer to an integer, which is named "locked". Which pointer should this be?

Lastly, regarding step 2 in section "3.5.2.3. Creating Partition 3 of the SD Card Image", in version 19.3 there is no "bsp-editor" within the embedded command shell. It is present in 19.1, but not 19.3. Futhermore, there is no folder named "hps_isw_handoff" within my base compilation? The guide pointed to by the manual https://rocketboards.org/foswiki/Documentation/A10GSRDGeneratingUBootAndUBootDeviceTree states that "(From 19.3 onwards U-boot would not be built from SOCEDS please look at CompilingLinux section for more information)". So can the SD card image be produced in 19.3, or should I go back and try the same steps in 19.1?

[MEIYAN_L_Intel]

Hi,

May I know after you see this "ERROR (phandle_references): Reference to non-existent node or label "led_pio"", are you able to generate the dtb file?

If yes, then you can ignore these error, however "led_pio" component cannot be toggle by linux system driver.

For the second error mentioned, according to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/aocl_rte_getting_started.pdf with chapter 4.1.4, the steps should help overcome these issues. Can you applied with this?

For the last question: yes, the bsp-editor is no longer available in 19.3, you should refer to rocketboard on how to create uboot on 19.3, or you can used older version(Quartus Prime Pro 19.1v) in order to used the bsp-editor.

Thanks

[CJohn56]

Hi,

Regarding the dtc command, yes the .dtb file is generated, so I will just ignore the errors.

Regarding the error when compiling the driver, yes as mentioned, I have already applied the fix stated in the manual. The manual fixes the error 'too many arguments' by calling 'get_user_pages_remote' instead of 'get_user_pages_unlocked'. However, after this fix, I get the error 'too few arguments'. In the newer version of Linux, it needs an additional pointer to an integer, which is named 'locked'. Since the original call is 'get_user_pages_unlocked', should it then just be a pointer to a 0? or something else?

Regarding the bsp-editor, I do not see a folder named 'hps_isw_handoff' within the base compile. Is this because I am using 19.3 where I should be using 19.1, or is there something else I should do? The guide on rocketboard states that '(From 19.3 onwards U-boot would not be built from SOCEDS please look at CompilingLinux section for more information)'.

[MEIYAN_L_Intel]

Hi,

According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_soc_eds.pdf stated: "The handoff settings are output from the Intel Quartus Prime Standard Edition compilation and are located in the / hps_isw_handoff/ directory (where is the HPS component name in Platform Designer (Standard)). You must update the hardware handoff files and regenerate the BSP each time a hardware change impacts the HPS, such as after pin multiplexing or pin assignment changes."

The handoff folder should be there when you compile the qsys which contains the HPS component, I would like to know whether the .qsys file have HPS component?

Thanks

[CJohn56]

Hi,

No there is no folder or subfolder called "hps_isw_handoff" in the base compile (the same directory where base.qdb or board.qsys resides). I have tried to open the board.qsys with Platform Designer, and from there generate the HDL files, still without luck. The board.qsys file does contain the "Hard Processor System Intel Arria 10 FPGA IP" (altera_arria10_hps).

[MEIYAN_L_Intel]

Hi,

The handoff folder should be available after you fully compile the quartus according to https://rocketboards.org/foswiki/Documentation/A10GSRDCompilingHardwareDesignLTS by clicking >-compiling hardware design as mentioned "~/a10_soc_devkit_ghrd/hps_isw_handoff - handoff folder, containing XML files used to generate the U-Boot device tree "

For the kernel driver, I am checking internally with kernel developer.

Thanks

[CJohn56]

Hi,

If I need to compile with Quartus, then I need a license right? I had one, but it expired in 2018 and I haven't had any use for the board until recently. Is there any way to invoke Quartus without a license? I.e. is there any way to start the compilation with aoc, where it will use the newly generated HDL files from Platform Designer? or should I look into renewing the Quartus license?

Regarding the driver: perfect!

[MEIYAN_L_Intel]

Hi,

For the OpenCL SDK , you do not need the license file.

For the Quartus, you need a license file for the compilation.

Thanks

[MEIYAN_L_Intel]

Hi,

There is an update for kernel driver from kernel developer. It seems like the locked parameter was added into the Linux kernel to make it compatible with get_user_pages_unlocked/get_user_pages_locked functions. If you pass in NULL to *locked for get_user_pages_remote() function, then it should be safe and behave like the old version.

Thanks

[CJohn56]

Hi,

It looks like the compiles without any errors, after adding NULL. Now there is only a warning:

a10soc_driver/aclsoc_dma.c:395:3: warning: statement with no effect [-Wunused-value] do_exit; ^~~~~~~

do_exit is a function. Should it be called, or should it just be ignored?

Is there any way to compile the modified base design using aoc (I.e. the OpenCL SDK)? I am also looking into refreshing our Quartus license for the board.

[MEIYAN_L_Intel]

Hi,

For question regarding the warning and do_exit, I will need to check internally with kernel developer.

For method to compile modified base design using aoc, you can check with the link below in Chapter 2:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/ug-aocl-a10pciedk-platform.pdf

To renew Quartus license, you can follow the steps as link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/education/demonstrations/online/licensing/how-to-renew-an-expired-license.pdf

Thanks

[MEIYAN_L_Intel]

Hi,

You can safely ignore that warning or delete that line and recompile. That line of code is the remnant of a port from older BSPs. There’s no need to call do_exit() function here. The compile warning occurs because the code is referencing the do_exit variable defined in one of the Linux kernel headers.

Thanks