What are you trying to accomplish by doing this?
Some IP, like the external memory interface IP, automatically enable or disable termination (on-chip termination) whether performing reads or writes and do the same to the ODT for the external memory.
I am connecting the FPGA to an external micro-controller. And depending on the program I am running on the micro-controller, I need to enable weak pull ups on the fpga pins. (Using external pull ups is not an option for me.). My fpga design is the same for every program I run on the micro-controller. Using several muxes I implemented on the fpga, I can change the FPGA configuration for different programs during runtime.
Right now because of the pullups, I need to build several versions of the design. But if I can enable/disable pull ups using some IP during runtime, I can keep a single bitstream.
The only thing I can suggest is adding logic that looks at what program is running and pulls up the appropriate I/O based on that. Even partial reconfiguration, which is only supported on high-end devices, reconfigures the core of the design, not the I/O.
Thank you for your reply.
Do you know how to pull up the appropriate I/O based on logic? This is what I am trying to figure out.
I could only figure out how to pull up a I/O using pin panner. But then I have to compile it to create a new bit stream. If can pull up the appropriate I/O based on some logic then I only have to compile it once.