Previously, I would parametrically define port widths based on localparams that are defined after the module port definitions, which I now realize causes errors during elaboration with certain tools (ModelSim, Active-HDL), but not others (Vivado).
Because I was switching full-time to Active-HDL, I transitioned to putting the localparam definitions in the module's parameter port list (which remedies the 'error' of the variable being used before it is defined). However, it seems as though Quartus does not like that, despite that usage being explicitly permitted in the SystemVerilog standard.
I'm using Quartus 20.1.1 Lite Edition.
(Yes, I have those files set to 'SystemVerilog' in Quartus. Yes, the localparams are listed last in the parameter port list.)
Now, if I turn those localparams into parameters, then it synthesizes fine. But that leaves the undesirable inevitability that somebody years from now (maybe me
Suggestions on how to use SystemVerilog files with Quartus in this way?
Thank you for the reply.
I get an error during Analysis and Synthesis with Quartus if I do:
module my_module #(
paramater TEST0 = 8,
localparam TEST1 = 16
input [TEST1:0] my_input
There error reads:
Error (10170): Verilog HDL syntax error at my_module.sv(5) near text: "localparam"; expecting an identifier ("localparam" is a reserved keyword ). Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Thank you very much for any help you can provide!