Error (10500): VHDL syntax error at mux5to1.vhd(15) near text "IN"; expecting an identifier ("in" is a reserved keyword), or a string literal what is the problem?

[gAcqu]

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY mux5to1 IS

PORT (x: IN STD_LOGIC_VECTOR(14 DOWNTO 0) ;

s : IN STD_LOGIC_VECTOR(17 DOWNTO 15) ;

f : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)) ;

END mux5to1 ;

ARCHITECTURE Structure OF mux5to1 IS

SIGNAL m0,m1,m2: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);

COMPONENT mux2to1

PORT( x,y: IN STD_LOGIC_VECTOR(2 DOWNTO 0) ;

             s : IN STD_LOGIC ;

             f : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ) ;

END COMPONENT ;

BEGIN

Mux1: mux2to1 PORT MAP

( x(14 downto 12),x(11 downto 9), s(15), m0(2 DOWNTO 0)) ;

Mux2: mux2to1 PORT MAP

( x(8 downto 6),x(5 downto 3), s(15), m1(2 DOWNTO 0)) ;

Mux3: mux2to1 PORT MAP

( m0(2 DOWNTO 0),m1(2 DOWNTO 0), s(16), m2(2 DOWNTO 0)) ;

Mux4: mux2to1 PORT MAP

( m2(2 DOWNTO 0),x(2 downto 0), s(17), f) ;

END Structure ;

[sstrell · Accepted solution]

SIGNALs do not have IN/OUT designations. It should be:

SIGNAL m0,m1,m2: STD_LOGIC_VECTOR(2 DOWNTO 0);

The error is pushed down to line 15 because that's the first line after this error.

#iwork4intel

[gAcqu]

thanks