Error: Can't run SignalTap II Logic Analyzer -- SignalTap II File is not compatible

[Altera_Forum]

Hi, 

I am trying to run SignalTap and see the signals but I get following error.   Error: Can't run SignalTap II Logic Analyzer -- SignalTap II File is not compatible with the file programmed in the device. The expected compatibility checksum value is 0x3015B694; the value read from device is 0x85F4DE2    I add a signal to signaltap and save it. Then I go to Quartun II (version 11.0 Build 208). I compile the design and start SignalTap again and program my device. As soon as I click on run analysis, in front of "Instance" and under "Status", it says "Not Compatible with the device"   Please let me know if you can think of any solution.   One option might be this. Somewhere in one of the threads, it says that .stp file is cached and it must be cleared. Do you how the cache in Quartus and signaltap can be cleared? Thanks

[Altera_Forum]

--- Quote Start ---  Hi, I am trying to run SignalTap and see the signals but I get following error.   Error: Can't run SignalTap II Logic Analyzer -- SignalTap II File is not compatible with the file programmed in the device. The expected compatibility checksum value is 0x3015B694; the value read from device is 0x85F4DE2    I add a signal to signaltap and save it. Then I go to Quartun II (version 11.0 Build 208). I compile the design and start SignalTap again and program my device. As soon as I click on run analysis, in front of "Instance" and under "Status", it says "Not Compatible with the device"   Please let me know if you can think of any solution.   One option might be this. Somewhere in one of the threads, it says that .stp file is cached and it must be cleared. Do you how the cache in Quartus and signaltap can be cleared? Thanks  --- Quote End ---    Hi,  I would close the signaltap file and re-open it again.  Kind regards  GPK

[Altera_Forum]

Other possible reasons: 

- the *.sof file downloaded by Signaltap is not the design you compiled last. Check the filename (and possibly folder) in the Signaltap window. - Your hardware is reloading the design from AS or other configuration memory after being configured. Disabling the on-board configuration controller may be necessary.

[Altera_Forum]

Hi Alexhugo, 

Typically, this error occur when you have modified the STP that require recompilation but you did not recompile the project or you did not program with the correct SOF which matches with your STP. Can you please try to delete db and incremental db folder and recompile the project with the STP see whether it helps or not? Make sure you choose the correct SOF before programming FPGA and running signaltap.

[Altera_Forum]

Removing the db directory didn't help. 

I checked the file names, closed and opened Quartus and none didn't help. can someone tell me how I can disable the on-board configuration controller and how I can clear the cache which may help! Thanks

[Altera_Forum]

In my case, it was because it chose the wrong .sof file. I checked the .sof file, chose the correct one, and it works. 

Hope that helps.  Regards, intan

[SBasa5]

I have ran into similar issue in Quartus Prime Lite 18.1.

I have created Signal Tap instance using: Tools->Signal Tap...

Compiled design. I can see sld_hub and sld_signaltap in hierarchy view (i can even locate it in chip planner after PAR)

Programmed device using sof.

In signal tap i have attached sof and it shows "compatible".

Signal Tap Logic Analyzer tool shows in red: "Start Rapid Recompile to continue".

Rapid recompile button is greyed out, using workaround: quartus_sh --flow recompile <proj_name>

Info (14904): Rapid Recompile skipped module Rapid Recompile Analysis & Synthesis because it is not required Info (14904): Rapid Recompile skipped module Rapid Recompile Partition Merge because it is not required Info (14904): Rapid Recompile skipped module Rapid Recompile Fitter (Place & Route) because it is not required Info (14904): Rapid Recompile skipped module Rapid Recompile Assembler because it is not required Info (293026): Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER Info (14904): Rapid Recompile skipped module Rapid Recompile Timing Analysis because it is not required Info (18207): Some modules have been skipped due to smart recompilation. You can turn off smart recompilation under Compilation Process Settings in the Settings dialog to fully recompile your design Info (293000): Quartus Prime Rapid Recompile was successful. 0 errors, 0 warnings Info (23030): Evaluation of Tcl script /opt/quartus/intelFPGA_lite/18.1/quartus/common/tcl/internal/qsh_flow.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings

Still nothing - cannot start my signaltap node.

Please help.

[sstrell]

Rapid recompile is only used/needed if you added/changed node usage in the .stp file after compiling the design. Otherwise, the .stp file should be compatible.

Even though it says to start RR, did you try just starting the logic analyzer running? If the file is compatible and you haven't made changes to the settings after compilation, it should work. I've seen weird status messages like that occur and the logic analyzer worked just fine.

#iwork4intel

[SBasa5]

Thanks for the answer.

My bad - I am modifying exisiting Cyclone SoC system. It is configured to boot from HPS side. After i have downloaded new FPGA config using JTAG: Linux rebooted the board and HPS bootloader overwritten my FPGA config.