Hi,
I want to simulate a simple test project for Cyclone 10 GX. My tool is Aldec Riviera PRO. I instantiate a PLL (IOPLL Intel FPGA IP) and a FIFO in Quartus 24.3 PRO. In Quartus the project compiles without errors.
In Riviera, I modified the Intel template script (attached) to control the simulation. When I run the script, I get the following error:
set TOP_LEVEL_NAME work.rockfish_devkit_top_tb
# work.rockfish_devkit_top_tb
set USER_DEFINED_ELAB_OPTIONS ""
elab
# [exec] elab
# ELBREAD: Elaboration process.
# ELBREAD: Warning: Cannot find library work_lib.
# ELBREAD: Elaboration time 0.3 [s].
# KERNEL: Main thread initiated.
# KERNEL: Kernel process initialization phase.
# ELAB2: Elaboration final pass...
# ELAB2: Create instances ...
# ELAB2: Fatal Error: ELAB2_0093 The defparam statement from module "cyclone10gx_iopll_ip" in "/rockfish_devkit_top_tb/c_dut/c_pll/iopll_0/altera_iopll_i/genblk1/c10gx_pll" points to variable "reference_clock_frequency" in a non-Verilog design region "/rockfish_devkit_top_tb/c_dut/c_pll/iopll_0/altera_iopll_i/genblk1/c10gx_pll/iopll_inst".
# ELAB2: Last instance before error: /rockfish_devkit_top_tb/c_dut/c_pll/iopll_0/altera_iopll_i/genblk1/c10gx_pll
# KERNEL: Error: E8005 : Kernel process initialization failed.
# VSIM: Error: Simulation initialization failed.
# SCRIPTER: Error: rockfish_top_tb.do : (55, 1): Script execution terminated due to error(s).
How can I solve this?
Best regards,
Julia Prigara
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Are you trying to use Verilog or VHDL for this and does your simulation tool support mixed-language designs?
It looks like you generated the PLL as Verilog but you're trying to compile in the sim tool as VHDL (or vice versa).
I use VHDL for my custom code and I generate all IPs as VHDL, picture attached.
Our Riviera PRO licenses support both VHDL and Verilog, picture attached.
The ELAB2_0093 Fatal Error seem to indicate that a mismatch in your design that arises because a defparam statement is trying to modify a parameter (reference_clock_frequency) in a module that is not defined in Verilog.
Some IP cores require the Verilog variant, as the VHDL version is not supported for certain IPs.
Could you try using the Verilog variant instead and check if the error is resolved?
Regards,
Richard Tan
Hi Richard,
thanks for the suggestion. I proceeded with overriding/forcing the PLL outputs from my testbench for now, as I am on a critical project line with this. I'll need to try out Verilog at a later point.
Best regards,
Julia
Hi Richard,
As it looks right now, I will just bypass the whole PLL for the rest of the project. I will not spend time on debugging this problem.
Best regards,
Julia
Thank you for the confirmation.
Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.
The community users will be able to help you on your follow-up questions.
Thank you and have a great day!
Best Regards,
Richard Tan
