How to ignore simulation only ports when mapping to FPGA pins?

[MoZdk]

A design has a number of simulation ports that should not be tied to FPGA pins. 

A VHDL example is shown in the source below, where the sim_only_* ports are for simulation only, thus should not be mapped to FPGA pins.

entity mdl is
  port(
    -- FPGA pins
    clk_i : in  std_logic;
    rst_i : in  std_logic;
    a_i   : in  std_logic;
    z_o   : out std_logic;
    -- Simulation pins only
    sim_only_in  : in  std_logic := '0';
    sim_only_out : out std_logic);
end entity;

The sim_only_* pins can be safely left unused by Quartus, since the inputs have default value.

When running Quartus, the mapper tries to map the sim_only_* ports to unused FPGA pins, which is not desired.

How can I specify that Quartus should just ignore the sim_only_* ports on the VHDL design?

[sstrell · Accepted solution]

Use Virtual Pin assignments in the Assignment Editor.  That way the logic for the pins will still be implemented but they won't get connected to physical I/O.

[RichardTanSY_Intel]

Hi @MoZdk 

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.