How to specify the 'Optimization Technique' in my System Verilog source code.

[BrianHG]

Hello,

     I would like to specify which 'Optimization Technique' to be used for specific .sv modules in my code.  I've tried:

/* synthesis CYCLONEII_OPTIMIZATION_TECHNIQUE = "SPEED" */

But quartus returns:

Warning (10335): Unrecognized synthesis attribute "CYCLONEII_OPTIMIZATION_TECHNIQUE" at ../BrianHG_DDR3/BrianHG_DDR3_PHY_SEQ.sv(52)

What's the proper way.

I would also like to disable 'Auto ram replacement' and 'Auto shift register replacement' for a few sections.  How do I go about this in my System Verilog Source code?

[sstrell]

These are not synthesis attributes.  These are assignments you'd put in your .qsf file, either manually or using the Assignment Editor, targeting the specific part of the design where you want them applied.

[BrianHG]

Thank you for answering.

I know about the .qsf and the Assignment editor.  However, such assignments will only be present if I supply an entire project.  I have developed SystemVerilog source code where I need specific modules to have specific settings depending on a set of parameters at the top of my code.  It is not efficient for me to begin to instruct all my third parties who use my code to begin to setup numerous assignments based on their parameter selection within their own project when they import my code into their design.

Is there no way to specify a number of synthesis settings within my .sv code?

[sstrell]

I don't understand.  You have parameterizable IP that includes parameters that can change how Quartus compiles the design?  The source files have to be a part of a project at some point.

I guess you could build a Tcl script that can be sourced by the .qsf file that can parse a design file and apply assignments as needed.  Or you can use the revisions feature in Quartus to create a single project and then, depending on which design files you use, you create appropriate assignments for each project revision.

Maybe I'm not clear on what your end goal is.

[BrianHG]

I'm only trying to provide an ASCII .sv source code file for others to use in anyway they like, IE: integrate my function into their own project.  I'm not trying to provide a complete Quartus project.

[SyafieqS]

Brian,

Assuming I understand your question correctly, have you consider to use preserve and keep attribute in Quartus? Maybe that's what you are looking for.

[BrianHG]

Hello SyafieqS_Intel,

     Thank you for recommending the (*preserve*).  It has solved the 'auto-generated alt_syncram' and 'auto-generated altshift taps'.  This allows my bus shift register to now exceed 300MHz as needed.  Now the only thing left is for the a method to assign the 'CYCLONEII_OPTIMIZATION_TECHNIQUE' which appears to vastly help with performance on some of my combinational logic.

     I wonder why the 'CYCLONEII_OPTIMIZATION_TECHNIQUE' is some sort of hidden synthesis setting deep in the menu separate of the normal compiler settings optimization mode which doesn't appear to do much for my code.

[ak6dn]

Whenever I have shared code with others that required additional setup such as you seem to need, I supplied a MODULE.qsf file along with the MODULE.v (in my case) file.

[SyafieqS]

Brian,

May I know if there is any update regarding this?

[SyafieqS]

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.