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Hi All,
My design has 3 hierarchies - H0, H1, and H2. The H0 is the upper one, under it H1, and H2 is under H1.
All the pins are currently assigned to H0 hierarchy.
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I'm not sure I understand what you mean by separate hierarchies here. Are you saying that H1 is instantiated in H0 (which is your top-level entity) and H2 is instantiated in H1?
When you say you want to write out the netlist of H1, what are you trying to get?
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Hi @amildm ,
Isn't it better to view the whole design netlist to get a better picture? May I understand why you want to write a specific design hierarchy?
If you are having trouble checking which netlist belong to which design, for example in RTL viewer, you may right-click > Locate Node > Locate in Design File.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
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Hi @amildm
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

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