Since you mentioned using Quartus v8.0 (for your info this software version is already obsolete), I'm assuming you are using old/mature FPGA device. At the PLL IP GUI you should be able to set the reference clk(input clock, inlclk0) value = 50Mhz and the output clock (C0) = 107Mhz. You can refer to the ALTPLL user guide from the link below for the details on how to use the PLL IP:
