Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Platform Designer: HDL blackbox automapping feature erroneous

PZ25
Beginner
805 Views

Hello

I try to import a core partition into my projects platform designer having a number of AXI MM and streaming I/F. I named the VHDL ports according to the conventions for automapping noted in

https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/name-hdl-signals-for-automatic-interface.html

However, all AXI I/F are importet as "streaming", even the memory mapped ones, resulting in wrong assignments.

Is there an addtional rule that separates MM from streaming?

Best reagrds,
Peter

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sstrell
Honored Contributor III
785 Views

Can you show your port HDL?  Something else must be going on here.

Also, I presume this is happening even after analyzing the HDL file(s) on the Files tab of the Component Editor?

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RichardTanSY_Intel
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Could you please try changing the Interface Type to your required setting and check if any error messages appear that might provide a clue?

capture.JPG

Best Regards,

Richard Tan

 

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RichardTanSY_Intel
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We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transition your inquiry to our community support.

We apologize for any inconvenience this may cause and we appreciate your understanding.

If you have any further questions or concerns, please don't hesitate to let us know.

Thank you for reaching out to us!


Best Regards,

Richard Tan


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