Platform Designer: HDL blackbox automapping feature erroneous

[PZ25]

Hello

I try to import a core partition into my projects platform designer having a number of AXI MM and streaming I/F. I named the VHDL ports according to the conventions for automapping noted in

https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/name-hdl-signals-for-automatic-interface.html

However, all AXI I/F are importet as "streaming", even the memory mapped ones, resulting in wrong assignments.

Is there an addtional rule that separates MM from streaming?

Best reagrds,
Peter

[sstrell]

Can you show your port HDL?  Something else must be going on here.

Also, I presume this is happening even after analyzing the HDL file(s) on the Files tab of the Component Editor?

[RichardTanSY_Intel]

Could you please try changing the Interface Type to your required setting and check if any error messages appear that might provide a clue?

Best Regards,

Richard Tan

[RichardTanSY_Intel]

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