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MAtte
Beginner
811 Views

Platform Designer fails to generate Verilog simulation model - "Error during execution of script generate_hps_sdram.tcl"

This problem recently started happening with my own project, but it can also be replicated with the DE10_Standard_GHRD project from Terasic's DE10-Standard_v.1.2.8_SystemCD. I am using Platform Designer 18.0 Build 614.

Generating Verilog for synthesis works OK, but if I enable generation of a Verilog simulation model, I get 92 error messages (more than I'm allowed to quote here, the full log is attached), and the simulation model seems to be incomplete and is not usable.

I'll put the start and end of the error list here:

Error: fpga_interfaces: Error during execution of script generate_hps_sdram.tcl: s0: Error during execution of "{C:/programfiles/altera/18.0/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally Error: fpga_interfaces: Error during execution of script generate_hps_sdram.tcl: s0: Execution of command "{C:/programfiles/altera/18.0/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt" failed Error: fpga_interfaces: Error during execution of script generate_hps_sdram.tcl: s0: Authorized application C:\ProgramFiles\altera\18.0\quartus\bin64\jtagserver.exe is enabled in the firewall. Error: fpga_interfaces: Error during execution of script generate_hps_sdram.tcl: s0: ]2;Altera Nios II EDS 18.0 [gcc4]C:/programfiles/altera/18.0/quartus/bin64/uniphy_mcc -ac_code sequencer_mc/ac_rom.s -inst_code sequencer_mc/inst_rom.s -ac_rom ../hps_AC_ROM.hex -inst_rom ../hps_inst_ROM.hex -header sequencer/sequencer_auto.h -vheader ../sequencer_auto_h.sv -ac_rom_init sequencer/sequencer_auto_ac_init.c -inst_rom_init sequencer/sequencer_auto_inst_init.c -DAC_ROM_USER_ADD_0=0_0000_0000_0000 -DAC_ROM_USER_ADD_1=0_0000_0000_1000 -DAC_ROM_MR0=0010001110001 -DAC_ROM_MR0_CALIB= -DAC_ROM_MR0_DLL_RESET=0010101110000 -DAC_ROM_MR1=0000001000100 -DAC_ROM_MR1_OCD_ENABLE= -DAC_ROM_MR2=0000000010000 -DAC_ROM_MR3=0000000000000 -DAC_ROM_MR0_MIRR=0010001101001 -DAC_ROM_MR0_DLL_RESET_MIRR=0010011101000 -DAC_ROM_MR1_MIRR=0000000100100 -DAC_ROM_MR2_MIRR=0000000001000 -DAC_ROM_MR3_MIRR=0000000000000 -DQUARTER_RATE=0 -DHALF_RATE=0 -DFULL_RATE=1 -DNON_DES_CAL=0 -DAP_MODE=0 -DGUARANTEED_READ_BRINGUP_TEST=0 -DMEM_ADDR_WIDTH=13 -DHARD_PHY=1 ... Error: fpga_interfaces: 2019.02.14.14:13:47 Error: Generation stopped, 10 or more modules remaining Error: fpga_interfaces: 2019.02.14.14:13:47 Info: hps_sdram: Done "hps_sdram" with 16 modules, 61 files Info: fpga_interfaces: "hps_0" instantiated altera_interface_generator "fpga_interfaces" Error: Generation stopped, 102 or more modules remaining Info: soc_system: Done "soc_system" with 62 modules, 114 files Error: qsys-generate failed with exit code 1: 93 Errors, 10 Warnings Info: Finished: Create simulation model

There are 20 lines of errors which start "Error: fpga_interfaces: Error during execution of script generate_hps_sdram.tcl", then it looks like it tries to continue but it hits another issue - "child process exited abnormally", but it's not clear what child process failed.

Does Platform Designer try to change firewall settings for jtagserver.exe? It's possible that the problem started when our network admin changed some management setting.

If anyone can even unpick what these error messages are trying to say, that would be appreciated.

Thanks,

Michael

 

 

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5 Replies
MAtte
Beginner
272 Views

Is it telling me that the error is coming from in nios2-bsp, which comes up at the end of both groups of error messages?

Error: fpga_interfaces: Error during execution of script generate_hps_sdram.tcl: s0: C:/programfiles/altera/18.0/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE Error: fpga_interfaces: Error during execution of script generate_hps_sdram.tcl: s0: child process exited abnormallyError: fpga_interfaces: 2019.02.14.15:16:55 Error: s0: C:/programfiles/altera/18.0/quartus/../nios2eds/sdk2/bin/nios2-bsp hal sequencer_bsp .. --default_sections_mapping sequencer_mem --use_bootloader DONT_CHANGE Error: fpga_interfaces: 2019.02.14.15:16:55 Error: s0: child process exited abnormally

 

AnandRaj_S_Intel
Employee
272 Views

Hi,

 

Trying to replicate the scenario but not succeeded.

I was able to successfully generate the Verilog simulation model for example project DE10_Standard_GHRD in Quartus 18.0 std & lite.Error is not related to design or tools.

 

Error during execution of script generate_hps_sdram.tcl: s0: Authorized application C:\ProgramFiles\altera\18.0\quartus\bin64\jtagserver.exe is enabled in the firewall.

The Error may be related to firewall.

 

Regards

Anand

 DE10GHRD-simGenQ18sd.jpg

 

 

AnandRaj_S_Intel
Employee
272 Views

+Log attachment

MAtte
Beginner
272 Views

Thanks for looking at this.

It would add up with what I have seen if the issue was to do with Quartus trying to set a firewall rule: this project used to generate OK for me too, and the start of the problem may have been when out network admin made some changes to the company network configuration.

I have checked that jtagserver.exe (same path as in the generate log) is enabled in the firewall for all network types, see below:

jtagserver firewall.png

but I note that I have to click on the 'Change settings' button with a shield icon on it before the firewall rules are editable - perhaps this means they are locked against being changed by software.

It seems a bit odd that the simulation model generation process wants to change firewall settings (and it fails if it can't change them even when they are already set correctly) but it would explain what I am seeing.

Now the question is what I can do to get things working again. Do I need to ask my network admin to change some management setting? Is there anyway I can tell Platform Designer to leave the firewall alone?

Thanks,

Michael

AnandRaj_S_Intel
Employee
272 Views

Hi Michael,

 

Firewall settings can interfere with the JTAG Server.

Can you please check with your admin once, We dont have any setting to tell Platform Designer to leave the firewall alone.

 

Regards

Anand

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