I am trying to set up a project with Quartus Prime Lite Edition 18_0.
I am importing the whole design and testbench with SystemVerilog Files, also for the design files. But in the EDA Tool Settings/Design Entry/Synthesis Window (Tool = Custom) i can't choose the option system format SystemVerilog. only Verilog , VHDL, AHDL; VQM can be choosen.
How can i change this so i can use SystemVerilog also for design file entry ?
That setting is for synthesizing your design in a tool other than Quartus. Are you doing that? If not, you don't need to set this. Quartus can synthesize .sv files directly.