Questa doesn't show UUT under Work

[jeffrs20]

This is for Quartus Prime Standard and Questa Sim (both licensed).

Under the test bench, the instantiated UUT should be present.  As I'm a novice I puzzled over what I was doing wrong.  However, I started a scratch project using a tutorial and got the same results (YouTube, Rania Hussein, Tutorial).  Aside from making syntax adjustments to use Verilog instead of System Verilog, I should have the identical results. 

Question - why is the UUT (and therefore the variables in it) not present?

thank you.

[sstrell]

Any screenshots?  Code?  Hard to figure out what's going on here without seeing anything you've done.

[jeffrs20]

Hello.  This is the simple tutorial source file.  This compiles without issues.  Attached is a screenshot of the Questa RTL sim, showing the testbench, but no DUT.

Thank you.

module fullAdder (A,B,cin,sum,cout);

input A,B,cin;

output sum, cout;

assign sum = A ^ B ^ cin;

assign cout = A & B | cin & (A ^ B);

endmodule

module fullAdder_testbench();

reg A,B,cin;

wire sum, cout;

fullAdder dut (A, B, cin, sum, cout);

initial begin

A = 0; B = 0; cin = 0; #10;

  cin = 1; #10;

B = 1; cin = 0; #10;

  cin = 1; #10;

A = 1; B = 0; cin = 0; #10;

  cin = 1; #10;

B = 1; cin = 0; #10;

  cin = 1; #10;

$stop;

end //initial 

endmodule

[sstrell]

You say "compiles without issues," but do you mean in Quartus or in Questa?  vsim only starts the simulator.  You have to first compile your code in the Questa GUI or with the vlog command.  You can generate a simulation script in Quartus that does this (Tools menu).

[jeffrs20]

Quartus completes the compile.  I attached a copy of the entire log but the final line is:

Info (293000): Quartus Prime Full Compilation was successful. 0 errors, 18 warnings

In Questa, here is a fresh RTL Sim called from Quartus.  I attached the log file showing the tb was compiled.

[sstrell]

Successful compilation in Quartus doesn't really matter for a simulation though it's still good to know it compiles successfully.

Now that you've compiled in Questa and started the simulation, you have to add waveforms to the Wave view and then actually advance the simulation (run command).

[jeffrs20]

Yes, I understand.  But I expect the DUT to be listed between fullAdder_testbench and #INITIAL#18.   I would select the DUT and the Objects would be listed, ready to be dragged into the Wave window.  However, no DUT is present.

Here is a screenshot of the YouTube tutorial.  Note that unlike my project, the DUT is present. 

[sstrell]

In Questa, you have to add the +acc option so the command is

vsim work.fullAdder_testbench -voptargs=+acc

In the GUI, this is

This is a change from Modelsim where this wasn't necessary.

[jeffrs20]

I found this option.  It looks slightly different than yours.  But when I change to Apply full...    The OK box is grayed out.   I also looked inside Quartus to see if there is an option to pass this to the simulator but couldn't find anything applicable.

[sstrell]

No, after compiling, do Simulate menu -> Start Simulation and click Simulation Options.  You also have to select the top-level design unit on the Design tab there.

[jeffrs20]

Ah.   That worked!   But why doesn't Quartus have an option to pass this option directly to Questa?

[sstrell · Accepted solution]

When you generate a simulation script for an IP or an example design, it does.

[jeffrs20]

Thank you very much!

Jeff