Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Similation

Okarin
Novice
337 Views
I have a project for cyclone 3. Can I send a verilogue code to the input of a circuit to get a simulation in modelSim?
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1 Solution
Kenny_Tan
Moderator
292 Views

Those are just the created testbench files, you can copy it and save it as .v.


Unfortunately, you vwf files does not have a place for you to store the testbench. If you want to do that, you may have to use modelsim instead.


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5 Replies
sstrell
Honored Contributor III
322 Views

Yes.  A testbench is typically code that is written as a "wrapper" around your design under test (DUT) that provides stimulus to the inputs and optionally monitors the outputs.

Okarin
Novice
313 Views
i created university program vwf, selected the required inputs and generated testbench. However, the file was created in .vwf.vht format, not .v
Kenny_Tan
Moderator
293 Views

Those are just the created testbench files, you can copy it and save it as .v.


Unfortunately, you vwf files does not have a place for you to store the testbench. If you want to do that, you may have to use modelsim instead.


Kenny_Tan
Moderator
267 Views

Any further queries?


Kenny_Tan
Moderator
253 Views

We do not receive any response from you to the previous reply that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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