Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Timing analysis - Timing requirements not met

germano
Beginner
1,483 Views

Hello,

 

When compiling my project I get two critical warning errors :

1. Critical Warning (14997): The FPGA to HPS SDRAM PLL reference clock path is not timing analyzed and could be subject to jitter.

2. Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.

In my Qsys, I use 50 MHz clock as well as a PLL with a 400 MHz output, in my constraint file I have (I'm new to timing contraints) :

# 50MHz board input clock
create_clock -period 20 [get_ports fpga_clk_50]

# create unused clock constraint for HPS I2C and usb1 to avoid misleading unconstraint clock reporting in TimeQuest
create_clock -period "1 MHz" [get_ports hps_i2c0_SCL]
create_clock -period "48 MHz" [get_ports hps_usb1_CLK]

derive_pll_clocks -create_base_clocks
derive_clock_uncertainty

I'm I missing something ? I don't understand those two error messages and what they want me to modify.

 

Thank you

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Nurina
Employee
1,464 Views

Hi,


What device are you targeting and what Quartus version are you using?

Can you share a screenshot of the clock connections in RTL viewer?


Regards,

Nurina


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sstrell
Honored Contributor III
1,448 Views

You're missing your I/O timing constraints, set_input_delay and set_output_delay.  All synchronous I/O need constraints.  Asynchronous paths should be set as false paths.  Run an analysis in the timing analyzer to see exactly which paths are failing timing.  I'd recommend starting here:

https://cdrdv2.intel.com/v1/dl/getContent/653046?explicitVersion=true

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Nurina
Employee
1,413 Views

Hi,


Does the above comment help?


Regards,

Nurina


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Nurina
Employee
1,399 Views

Hi,


We do not receive any response from you on the previous reply provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey


Regards,

Nurina


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