Hello,
When compiling my project I get two critical warning errors :
1. Critical Warning (14997): The FPGA to HPS SDRAM PLL reference clock path is not timing analyzed and could be subject to jitter.
2. Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
In my Qsys, I use 50 MHz clock as well as a PLL with a 400 MHz output, in my constraint file I have (I'm new to timing contraints) :
# 50MHz board input clock
create_clock -period 20 [get_ports fpga_clk_50]
# create unused clock constraint for HPS I2C and usb1 to avoid misleading unconstraint clock reporting in TimeQuest
create_clock -period "1 MHz" [get_ports hps_i2c0_SCL]
create_clock -period "48 MHz" [get_ports hps_usb1_CLK]
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
I'm I missing something ? I don't understand those two error messages and what they want me to modify.
Thank you
