Timing requirements not met inspite of optimised design.

[SKGR0]

I have been using a design on Cyclone V device.

I use Quartus Prime 16.1.2 for compilaiton.

The resource and logic utilisation is not above 50 %.

What I observe is the timing requirements is not met for the system. I have checked the paths with slacks and improved the timing in those paths . But later again the timing is not met showing other paths which are not involving high logic / complex wiring.

The timing is achieved after number of trials with different initial placement seed in fitter settings. But it is a tedious to run multiple compilation of the system as it takes hours to finish compilation.

I have even tried different versions of Quartus. The behaviour is the same.

Is there an alternate solution for this situation to achieve timing without changing the design?

[sstrell]

Can you provide the design or describe what part(s) of the design are failing timing and by how much? Can you provide your .sdc file? Are you using physical placement constraints such as Logic Lock regions? It's hard to help optimize a design without seeing the design itself.

#iwork4intel

[KhaiChein_Y_Intel]

Hi,

Could you provide the design for investigation?

Thanks.

[KhaiChein_Y_Intel]

Hi,

May I know if you have any updates?

Thanks.

Best regards,

KhaiY

[SKGR0]

Im sorry , I will not be able to share the design

Sorry for the late reply