Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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auto-generated file "is missing"

HenryMittel
Beginner
1,046 Views

I created a copy of a working design (because I need to move to the newer Arria 10 family), modified the Qsys (because it uses hard-IP that is different for the new family), adapted the wrapper for the Qsys component, dropped that into my main design, and I am trying to compile.

While "generating" the Qsys, there was only one warning (some setting for a Flash are 'ignored').

I am currently compiling with the option turned on to "Generate Qsys" during the compilation (not exactly by choice, but because this or other errors occur).  While compiling the whole design I get a message:

12019 Can't analyze file -- file ... is missing.

The '...' in the line above happens to be:

Qsys/altera_avalon_sysid_qsys_150/synth/Qsys_altera_avalon_sysid_150_3mfnmli.v

The SYSID is an Intel/Alter component, i.e. not something I screwed up.  The file seems to be  auto-generated.  In other attempts of the compilation, this error occurred with other strings instead of "3mfnmli".

The 'Project Navigator' page 'IP components' lists this file, but with "7jjminq" as that variable string.  The referenced folder has such a file but currently with "d3fan3a" as the variable string.

How is it possible that an auto-generated file (generated a minute before it is needed) is missing?  Well, more importantly, what can I do about it?

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HenryMittel
Beginner
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Hello sstrell,

Thank you for explaining the difference between including .qsys and .qip in the settings file.  I thought the "IP Regeneration Policy" under "IP Settings" in Assignments | Settings would decide about that.

While your answer wasn't directly helpful, it prompted me to take an Nth look at the IP Settings page ... and give "Verilog" instead of "VHDL" another try.  I also turned off the regeneration and manually regenerated (as Verilog) the system in the Qsys designer.  Now, the errors with the auto-generated files are gone - and I can start working on the errors I introduced.

 

And yes, I am still using the old Quartus 15.0 - because I was told that my RapidIO license, whose maintenance expired in 2015, can only be used with Quartus 15 or earlier.  Should I question that advice?

Thanks for the assistance with the original problem.

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sstrell
Honored Contributor III
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I'm presuming you are using the Standard edition of Quartus.

Which Qsys (now called Platform Designer) file have you added to your Quartus project: .qsys or .qip?

If you want the system to get automatically (re)generated every time you compile your Quartus project, add the .qsys file to your project.

If you want to manually generate your system every time you make a change, do that in Qsys (Platform Designer) and then add the generated .qip file to your Quartus project.

This error sounds like an issue with the system not getting auto regenerated, so try manually regenerating in Qsys (Platform Designer) and adding the .qip to your project.  The strings you mention are randomly generated and get listed in the .qip file, so perhaps Quartus is not seeing the updated file names because of an old .qip.

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HenryMittel
Beginner
1,027 Views

Hello sstrell,

Thank you for explaining the difference between including .qsys and .qip in the settings file.  I thought the "IP Regeneration Policy" under "IP Settings" in Assignments | Settings would decide about that.

While your answer wasn't directly helpful, it prompted me to take an Nth look at the IP Settings page ... and give "Verilog" instead of "VHDL" another try.  I also turned off the regeneration and manually regenerated (as Verilog) the system in the Qsys designer.  Now, the errors with the auto-generated files are gone - and I can start working on the errors I introduced.

 

And yes, I am still using the old Quartus 15.0 - because I was told that my RapidIO license, whose maintenance expired in 2015, can only be used with Quartus 15 or earlier.  Should I question that advice?

Thanks for the assistance with the original problem.

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SyafieqS
Moderator
981 Views

Hi Henry,


From the link below, I can see RapidIO will be discontinue on 2020-2021. Therefore, Quartus 20.3 should still be available.


https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_rapidio.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pcn/pdn2025.pdf



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SyafieqS
Moderator
944 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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