signaltap and mismatch between RTL simulation and signaltap

[Altera_Forum]

I am new to signaltap and also had some questions. 

 I have this code ... always @(posedge signal_delayed_2 or negedge reset_n) begin  if (!reset_n)   start_signal1 <= 8'h00;   else   # 1 start_signal1 <= counter;    end  always @(negedge signal_delayed_2 or negedge reset_n) begin  if (!reset_n)   stop_signal1 <= 8'h00;   else   # 1 stop_signal1 <= counter;    end  My counter rolls over after 2**10  In RTL and gatelevel simulation it works fine and in signaltap and on o-scope it shows different values for start_signal1 (+- 2) from actual values, even though I am feeding a constant pulse to signal which is delayed by 2 clocks for synchronization).  Please let me know if you have ideas/suggestions.

[Altera_Forum]

Your problem is not clear. But I observe: 

your clk named signal_delayed_2 sounds gated...beware of gated clk problems. your# 1 is ignored in synthesis if your start_signal1 is delayed by 2 clks then it will follow counter by two clks leading to +-2 difference depending on how you are kicking the counter...

[Altera_Forum]

I am getting signal_nodelay (asyncronous to my clock) and then I pass it through 2 flip-flops for synchronizing it to my clock. 

The counter is running synchronized to the clock.  so if the posedge of signal_delayed_2 occurs when counter = xAA2 signaltap would sometimes report that start_signal1= xAA0 or xAA4 or xAA2 at various samples.  also wouldn't I delay the assignment of counter to start_signal1 by 1 timeunit after the posedge of signal_delayed_2

[Altera_Forum]

There isn't enough information I am afraid. 

 All you have is start_signal1 chasing counter(one register in between). Ofcourse start_signal1 should follow counter by one clk edge. But is your signaltap sampling clk correct and is there anything else driving start_signal1. You better post all your code to see what you have done!