10M04SCU324I7G - Timing files

[chris_gonzalez9]

Is there any timing files for MAX 10 - 10M04SCU324I7G FPGA? I'm trying to make a timing analysis using timing designer, but I can't find these timing file constrains. 

[sstrell]

You mean a .sdc file?  You have to create that yourself for your design.

[Kenny_Tan]

I would suggest you take a look into the wiki when you want to start writting your constrain:

https://community.intel.com/t5/FPGA-Wiki/Timequest-Static-Timing-Analysis/ta-p/735556

https://community.intel.com/t5/FPGA-Wiki/Timing-Constraints/ta-p/735562

[chris_gonzalez9]

Thanks for your feedback. I already have all the timing constrains, but it will be best if we can have a timing file (.sdc or .td) instead of making it from scratch. I think it's under Cyclone 10 LP Devices.

[sstrell · Accepted solution]

Again, you have to create this for your design.  It's not created for you because the tool has no way of knowing what your timing requirements are.

[Kenny_Tan]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.