10M04SCU324I7G - Timing files

[chris_gonzalez9]

Is there any timing files for MAX 10 - 10M04SCU324I7G FPGA? I'm trying to make a timing analysis using timing designer, but I can't find these timing file constrains. 

[sstrell]

You mean a .sdc file?  You have to create that yourself for your design.

[KennyTan_Altera]

I would suggest you take a look into the wiki when you want to start writting your constrain:

https://community.intel.com/t5/FPGA-Wiki/Timequest-Static-Timing-Analysis/ta-p/735556

https://community.intel.com/t5/FPGA-Wiki/Timing-Constraints/ta-p/735562

[chris_gonzalez9]

Thanks for your feedback. I already have all the timing constrains, but it will be best if we can have a timing file (.sdc or .td) instead of making it from scratch. I think it's under Cyclone 10 LP Devices.

[sstrell · Accepted solution]

Again, you have to create this for your design.  It's not created for you because the tool has no way of knowing what your timing requirements are.

[KennyTan_Altera]

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