Broken JTAG-chain Cyclon V SoC

[Mathias3]

Hello

Issue: In our design with a Cyclone V SoC 5CSXFC6D6F31I7N we have the JTAG-chain: HPS->FPGA. With the Quartus Prime Programmer Standard Edition und USB-Blaster (terasIC) we see a JTAG-response from the FPGA (see attached screen shot), however, none from the HPS. We find this behavior on both prototype boards, and therefore do not assume a random soldering issue.

Analysis: Using an oscilloscope, we find that HPS_TDI, HPS_TCK, HPS_TMS and TCK, TMS, TDO seem fine, i.e. at least change states. Unfortunately, we do not have access to HPS_TDO and TDI as they are routed directly. The MSEL[0..4] are set to GND and we verified the power supplies on the different banks. See our schema in attachment.

Questions: is the JTAG-chain HPS->FPGA the correct choice? And if yes, are there any special requirements or settings to consider for this configuration? Is there another test we could do to localize the issue?

Many thanks for any hints.

Cheers

Mathias

[sstrell]

I think you have your connections backwards.  You have JTAG_TDI going to HPS_TDI.  I think you should have JTAG_TDO going to HPS_TDI and JTAG_TDI going to the FPGA's TDO, unless this is just a naming issue in your design (which looking at it again I think it is).

I'm going by the DE1-SoC schematics from Terasic (download the "CD-ROM"): https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=836&PartNo=4#contents 

Also note that MSEL all low means you're doing an HPS boot-first setup, meaning the HPS is responsible for programming the FPGA after it boots.  I don't know if that's a part of this issue, but FYI.

[thom62]

Hi

we see the FPGA within the chain, I don't think we have a crossover issue in our design:

Best regards

Thomas (working with Mathias)

[mabdrahi]

Hi Mathias,

I will try to look on your setting base on what document we have,

Staytune

Thank you,

Aliff

[mabdrahi]

Hi Mathias,

May i know, are you using custom board?

What is quartus version are you using?

Thank you,

Aliff

[thom62]

Hi Aliff

Yes we work with our own design, attached you find the schematic about how we connect to JTAG. Probably this helps.

Best regards

Thomas

[mabdrahi]

Hi Mathias,

Can you change the new JTAG cable?

I think we have this issue before that cause by cable it self.

Thank you,

Aliff

[thom62]

Aliff

Today we receive a new USB Blaster, the latest version from Intel, I'll make tests with it. Yesterday I made tests with the old one from terrasic and got the following result:

Then I made tests with a Segger J-Link J-TAG interface and its corresponding J-Link Commander app. This test has been performed with a 4MHz TCK clock and I got the same result on TDO: 0xFFFFFFFFFFFFFD55 while scanning the instruction register.

SUMMARY: two custom boards in our lab show the same behavior, two complete different tools also show the same results, TCK frequency has no influence to the measured results.

I think the HPS J-Link is not working in our setup.

best regards

Thom

[thom62]

Hi Aliff

we can close this support request! +1.1V for the HPS system was not working as expected. For this reason the J-TAG chain was not working properly in the HPS part. From the beginning I was pretty much sure that this might be the reason but I couldn't find the source..

Thank you very much for your time and help..

Best regards

Thom

[NurAiman_M_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.