Design with Logic Lock region cannot fit anymore Error (18999): Placement cannot find a legal solution

[avk]

Hi,

I have a design using two logic lock regions for timing optimization. Unfortunately Quartus would not fit the design when I assign the entity to the LL regions throwing this error during fitting:

Error (18999): Placement cannot find a legal solution

I cannot find any more information that would help me solve this issue. Any hints?

I am using Intel Quartus Standard Edition 18.1.0.Build 625 on a Win10 Machine.

[sstrell]

Using LL limits placement options for the Fitter. Before choosing to use LL regions, try compiling with no LL regions set. See what you get for a placement from the Fitter. Then, if you are still having timing issues, look at other solutions, such as verifying your timing constraints and using optimization settings before looking at LL regions. If you still want to use LL regions for organization or to force logic to a certain part of the chip, try creating a floorplan similar to what the Fitter selects on its own when no regions are enabled. Floorplanning is more of an art than a science so it can be difficult to find a working floorplan for a high-speed design. Unless you really need to use them (such as for flows that require them like partial reconfiguration), there's not as much reason these days to use them. The Fitter does a pretty good job on its own.

#iwork4intel

[Kenny_Tan]

Here are the document for create floor plan. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii52006.pdf

You can also make the logic lock region larger to see if it fits.

[Kenny_Tan]

Any update?

[avk]

Hi,

Thanks for your replys. I know i can make the LL region larger, the strange thing is, that this issue popped up when I removed quite a large part of my former design that moved to the HPS. Placement should now be much more relaxed than before, so this should not have happened. However, I will give it a try with a larger region.

Furthermore I find the error message not very helpful. A hint which region caused the fail would come very handy.

[Kenny_Tan]

Can you attached your design.qar? We can feedback on the error message improvement. You can attached it here or attached private to us. You may check your email. Thanks

[avk]

I am not allowed to share this design due to customer restriction, sorry

[Kenny_Tan]

It's ok, try to make it larger and let us know how it goes. Another way is let the logic lock float. Quartus will decide how large it need to place. thanks

[Kenny_Tan]

Any update?

[Kenny_Tan]

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