FPGA JTAG Circuit for Cyclone II

[alparodi]

Hi. I am developing a Cyclone II - EP2C20AF256I8N FPGA schematic using the EPCS16SI8N memory. I wanted to know if the following schematic is correct to program it through USB BLASTER ALTERA CPLD. If I have any mistake, could you please correct me?
Is it necessary to put the two headers to record it also by AS?

[FvM · Accepted solution]

Hello,
the configuration interface is implemented correctly. You don't need a second AS header, flash will be programmed through JTAG by using JTAG indirect configuration.

[NurAiman_M_Intel]

Thank you FvM for sharing the solution.

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