Fitter resource usage summary

[Altera_Forum]

Hi  

 I get the following utilization in Fitter resource summary:   that Clock pins - 3/2(150%)  Dedicated Input pins 7/4 (175%)  What does this exactly mean? Does this mean 3 clock pins are being used out of 2 and & dedicated pins are being used out of 4 But how can this be possible when there are 4 dedicated pins available or 2 clock pins available??  Is something going wrong?

[Altera_Forum]

It suggests your design needs more input resources than the device you've selected has available. Without a little more context the consequence of this is difficult to judge. What device are you targeting and, roughly, what is your design trying to do? 

 Cheers, Alex

[Altera_Forum]

Thanks Alex 

 The device I am using has more I/O pins and the design only needs one clock pin; the fitter is choosing these pins for some reason I can always change them in Pin Planner to other User I/O pins and make the clock and dedicated pin free. I mean if it is not coming as Error(red) should this be a problem  I don't understand if the device has only available two clock pins how can it use 3??

[Altera_Forum]

How far through compilation does the project get? Can you post some of the report files generated when you run through project through Quartus? The "{}.sta.rpt" & "{}.fit.rpt" should do. 

 It's not clear from what you've written whether there's an issue. The fitter may chose to use dedicated clock input pins for non clock signals.  Cheers, Alex

[Altera_Forum]

Hi Alex 

 Thanks very much. The compilation goes to 100 percent without error.  I am not using any constraint files. I am using quartus ii 9.0 SP2 and I am not able to see any {}.sta.rpt file for some reason.Although I am attaching the {}.fit.rpt  I/O pins ; 148 / 406 ( 36 % ) ; ; -- Clock pins ; 3 / 2 ( 150 % ) ; ; -- Dedicated input pins ; 7 / 4 ( 175 % )   Thanks very much for all your help

[Altera_Forum]

--- Quote Start ---  Hi Alex  Thanks very much. The compilation goes to 100 percent without error.  I am not using any constraint files. I am using quartus ii 9.0 SP2 and I am not able to see any {}.sta.rpt file for some reason.Although I am attaching the {}.fit.rpt  I/O pins ; 148 / 406 ( 36 % ) ; ; -- Clock pins ; 3 / 2 ( 150 % ) ; ; -- Dedicated input pins ; 7 / 4 ( 175 % )   Thanks very much for all your help  --- Quote End ---    to me it is a reporting bug, unless tool has got super clever and we can't spot it. But I think 150% is more than 100%

[Altera_Forum]

Thanks Kaz 

 Alex, however I am attaching {}tan.rpt (timing analyser report) instead of {}.sta.rpt. Thanks

[Altera_Forum]

Have you tried running the assembler?

[Altera_Forum]

I agree with Kaz - this appears to be a reporting bug. The timing report has correctly identified one clock. 

 Given the age of the family you're using I think it's pointless reporting it to Altera.  Cheers, Alex

[Altera_Forum]

Thanks very much. I also thought so

[Altera_Forum]

Out of interest, have you tried compiling the design with Max Plus 2? 

A few years ago when I had to modify a 15 year old Flex10k design, I tried porting it to Quartus 9. During the fitter it told me that some Ram configuration was illegal for the Flex, but it compiled without problems in Max Plus2. So I stuck with that.

[Altera_Forum]

No not yet. Will do. 

 One more thing. I am not able to find EPF10K100 which is a Flex10K device anywhere. I tried no. of altera software including max plus 2 but the last Flex10K device that I see is EPF10K70??  Cheers