How to guarantee stable data when altsyncram and state machine use same clock?

[Joes19]

Hi everyone,

I'm looking to modify a top level design that uses a relatively simple computation module with some muxing and addition inside. All levels of the design run on a single positive edge clock. Instead of a single computation, I need to modify it to add roughly 100Kb memory. The controller will load inputs from memory, compute, and save the outputs to memory.

I created a small state machine to model the dual port ram using altsyncram component (generated by wizard using multiple M9k or M144K ) based on a similar example. Everything operates correctly in simulation but all the data, addr, we transitions line up with the positive edge of the clock which the ram component is using to write to memory. I can add a clock cycle before and after write enable so the addr/data are stable, but that triples the computation time of each iteration… not a huge deal but not desirable given the number of computations.

Coding guidelines prevent me from inverting the clock or using falling edge logic, so I’m trying to find another way to guarantee stable data without adding too much delay. I didn’t see a way to configure the ram for the other edge (using Quartus 14.1 megawizard, stratix IV fpga). I also considered trying to adjust the timing of the enable, but the design needs to be portable to 4 different stratix/cyclone fpgas so I’d like to keep it simple. Worst case I can live with adding delay states, but I’m wondering if anyone has ideas to solve this more elegantly.

Thanks

[ak6dn · Accepted solution]

ALTSYNCRAM is a synchronous SRAM block, the output data is registered using the outclock. The input data/address/control is registered using the inclock. Connect inclock and outclock to the same source clock to use it as a fully synchronous SRAM. You then just need to meet setup/hold requirements for all the registers and adhere to maximum clock frequency limits for the device (ie, to guarantee SRAM access time met). These are NOT like discrete ASYNC SRAMs which I believe you are comparing them to.

[Joes19]

Thanks! I just went back into the megawizard and toggled the option to register outputs with input clock. I'll give it another try, don't mind the pipelined outputs if it saves me from a complicated memory write procedure.