Integer to Bit Vector VHDL code error

[Altera_Forum]

I'm new to VHDL and I am trying to convert an integer to a 14 bit vector. Here is the protion of my code. 

  gear_calc <= to_integer(unsigned(to_stdlogicvector(Input_2)));    synchro_gear <= gear_calc*36;    IF synchro_gear < 360 THEN  FOR i IN 0 to 16383 LOOP  synchro_gear_vect(13 DOWNTO 0) <= bit_vector(to_unsigned(synchro_gear,i));  END LOOP;  END IF;  This is the error I get when I try to compile the code:   Error (10305): VHDL Type Conversion error at gearbox.vhd(76): cannot convert type "UNSIGNED" to type "bit_vector"  The libraries I'm using are here:   USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL;   Any help would greatly be appreciated. Thanks:)

[Altera_Forum]

--- Quote Start ---    FOR i IN 0 to 16383 LOOP  synchro_gear_vect(13 DOWNTO 0) <= bit_vector(to_unsigned(synchro_gear,i));  END LOOP;  END IF;   --- Quote End ---    above loop will be unrolled by compiler to last case of i = 16383. All other cases will be overwritten.  regarding bit_vector, change them to std_logic and you are avoiding the old type

[Altera_Forum]

to_unsigned() takes a bit length as second parameter, it must be 14 in this case. A to_stdlogicvector() or to_bitvector() conversion has to be applied on the unsigned then.

[Altera_Forum]

So do I need to shift the bits over as they are read into the synchro_gear_vect() bit vector to get a full 14 bit resultant?

[Altera_Forum]

You better explain fully to the forum what is your input, what do want to do to it and what output want to get. Otherwise we will be going in circles.

[Altera_Forum]

I was able to figure it out using what FvM said and not using the FOR loop. Thanks for the help!!!:)

[Altera_Forum]

why are you using bit_vectors anyway?  

Second question, why are you doing such massive conversions? why not just stick with integers or unsigned?  This amount of type conversion can get very frustrating when you have to do it all the time. Its alot easier just to stay with the type, and keep associated signals in simular types.

[Altera_Forum]

I decided to use std_logic_vectors and the reason bieng is that my inputs and outputs to my code are in parallel 14 bit strings, and I have to do some arithmetic and calculations with the inputs to come up with some ofthe outputs, so I thought it would be easier to do the calculations in integer types and convert back to bit vectors before I output.

[Altera_Forum]

Port maps can have unsigned/signed type or even integers in them, you dont have to stick with std_logic/std_logic_vector, or even worse, bit vectors, especially if its an embedded entity (ie not directly connected to pins). For the top level its best to stick to some array type, but you can still use unsigned/signed to avoid all that annoying type conversion.

[Altera_Forum]

So I can use integers to do all my calculations and even type my inputs and outputs as integers? If I do that do I have to put a range on my integers because I only want a 14 bit value on my outputs?

[Altera_Forum]

yes, you can use integer for entity input and outputs (but not at the top level). And yes, giving it a range of 0 to 2**14-1 will limit it to 14 bits. If you dont put a range, it will use 32 bits, but if the top bits are never connected to anything, they should be snipped during synthesis. But putting a range is normally the safer option.