we have data path : RAM output->normal_reg->DSP_input_reg ,
there is only one "normal_reg" , but it drives 8 DSPs, timing violation path reported for "RAM output->normal_reg".
without insert clock cycles , what can we do to fix it?
maybe move the "DSP_input_reg" outside DSP block helps? i do not know how to constrains it on RTL, or some other suggestions?