Some questions of PCIe video capture card solution using EP4CGX15.

[Altera_Forum]

Hello,everyone. 

Our case needs a FPGA to transfer video buffer to our ARM SOC.  And the video mode is till to 1080P30,the FPGA using is EP4CGX15.  The IDE using is Qsys v12.0    The block diagram is just like below:  8Bit BT.656 PCIe×1 Gen1  ASIC-------------------> EP4CGX15 ----------------> ARM SOC   The maxim clock rate of BT.656 data to EP4CGX15 is 148.5M;   And I think the internal logic in EP4CGX15 is just like this:  Avalon-ST Avalon-MM Avalon-MM  ASIC-------> Clocked Video Inut (IP)------------->FrameBuffer(IP)----------------->SGDMA(IP)----------------->PCIe(IP)---------->ARM SOC   If ARM soc send an start order to FPGA,and then the FPGA start to send a entire frame buffer to ARM soc,the buffer is till to 6,220,800 bytes.  After this the operation repeats.   FPGA doesn't process the video buffer,just act as a "bridge".   Could our FPGA work without problem?   Thanks for any answers.

[Altera_Forum]

After post the thread to the forum,the word format was changed......

[Altera_Forum]

Post Your Data flow as attached picture and maybe someone answers. 

I'm also interested in Your case )

[Altera_Forum]

--- Quote Start ---    FPGA doesn't process the video buffer,just act as a "bridge".  Could our FPGA work without problem?   --- Quote End ---   What do You mean - FPGA doesn't process the video buffer,just act as a "bridge" ? Does EP4CGX15 work without problem for Your block diagram?