Programmable Devices

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Programmable Devices

Discussions

Serial Transceiver Data Rates for Export Control reason

CycloneII I/O pin damage (Short to VCC)

SERDES in Stratix II

cyclone v gt has pcie phy?

Altera FPGA LED switches OFF after loading the sof file

Arria V: VOD values for LVDS i/o

Cyclone lll emulated LVDS IO

Measuring delay from a PLL output to an FPGA pad

ALTLVDS external clock

urgent help

EPC8 support discontinued in new version of Quartus

Stratix II EP2S60 jack 3,5mm

Where er the PDF documents for Cyclone 5

Cyclone V LVDS fractional PLL

It is worse to assign clock on different bank or on non-clock input pin?

Featured Content

Quartus Prime Design Software - JTAG usage

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

EPM3064ATC44-7N and EPM3064ATI44-10N

Re: Download speed

Re: Quartus Prime Design Software - JTAG usage