Programmable Devices

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Programmable Devices

Discussions

DDR2 Timing Problem in Nios System on Stratix III dev.board

1.5 PCML lines not appearing in IBIS file

How to receive LVDS ADC data

Altera DE2 jtag issues

OCT on Cyclone III

I/O states in Cyclone III in JTAG mode

uClinux on nios2 with Serial RAPID I/O

Is the AD/DA converter Cyclone 3 starter kit compatible

sdr sdram vhdl controller

Need advice on device/kit for NTSC video project

VHDL Code-Multiplication

DAC with serial SPI interface

cyc iv: using 3V I/O standard with VCCIO=3.3V

FPGA INTERFACING with ADSP BF548?

Using an address to access registers

Featured Content

LPM_MULT not working for Cyclone 10 GX device

Need help with timing constraints/closure for an EMIF design

Error running Agilex 5 LPDDR4 example design simulation

I350 igb driver failed with error -2

Request for the Product Lifecycle Status

Solution: USB Blaster Driver for Windows 11 ARM

Re: Where can I find a reliability report for Cyclone 10 LP devices?

Re: MAX10 (Select Internal Configuration mode with ERAM )