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Hey,
I'm using a 10M16SAU169I7G with "Dual Configuration" IP-Core. There is 1 Clock in the design and its rate is ~14[MHz].
Timing analysis process:
At first, I got this warning:
- After setting "ru_clk" to the same rate as "CLK_UART", I got a 'Failing path' warning when the Lanch Clock is the "ru_clk" and the Latch clock is the "CLK_UART". when I click on "Locate node in the design file", I'm taken to the IP-Core design files.
I don't understand how to fix this problem.
Thanks.
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Did you set the clock frequency appropriately in the parameter settings for the IP? Can you show your .sdc?
And this single clock is the only clock in your entire design? Can you show the details of the failing timing path from the timing analyzer?
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This might be related to the KDB below:
Could you try to use the timing constraint stated in the KDB so that the RU_CLK runs at half the rate of the input clock.
https://www.intel.com/content/www/us/en/support/programmable/articles/000080607.html
FYI, the MAX 10 FPGA Configuration User Guide states that the Altera Dual Configuration IP generates RU_CLK that runs at half the rate of the input clock.
Best Regards,
Richard Tan
p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.
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Dropping a note to ask if my last reply was helpful to you?
Do you need any further assistance from my side?
Best Regards,
Richard Tan
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We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support.
We apologize for any inconvenience this may cause and we appreciate your understanding.
If you have any further questions or concerns, please don't hesitate to let us know.
Thank you for reaching out to us!
Best Regards,
Richard Tan
p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.
