Sometimes I found that timing reports in Timing Analyzer differs from timing Summary in Compilation Report.
For example, the Setup Summary at 900mV 100C corner is following figure.
The first one is PCIe clock, and slack is -0.693ns.
But, when I open Timing Analyzer and report timing of this clock,
it shows no timing violation.
The worst path is 0.048ns:
Does anyone know the reason?
That's certainly strange. Can you right-click the failing clock(s) in the compilation report and generate a timing report from there? Perhaps your report_timing command is not exactly matching up with what is shown as failing in the Compilation Report.
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