Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18458 Discussions

timing report in quartus

CHung
Novice
185 Views

Hi,

Sometimes I found that timing reports in Timing Analyzer differs from timing Summary in Compilation Report.

For example, the Setup Summary at 900mV 100C corner is following figure.

CHung_0-1597197097094.png

The first one is PCIe clock, and slack is -0.693ns.

But, when I open Timing Analyzer and report timing of this clock,

it shows no timing violation.

CHung_2-1597197417781.png

The worst path is 0.048ns:

CHung_1-1597197146423.png

Does anyone know the reason?

Thanks.

0 Kudos
3 Replies
sstrell
Honored Contributor II
168 Views

That's certainly strange.  Can you right-click the failing clock(s) in the compilation report and generate a timing report from there?  Perhaps your report_timing command is not exactly matching up with what is shown as failing in the Compilation Report.

#iwork4intel

CHung
Novice
160 Views

Hi @sstrell 

You are right.

The command generated from compilation report is different from mine.

My report_timing command set both startpoints and endpoints.

Thanks.

KhaiChein_Y_Intel
148 Views

Hi,


Since your question has been answered, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY


Reply