Fitter Error with Quartus Prime 18.0 for HPS_CLK1

[scong4]

I use HPS_CLK1 as system clock , but can't assign it .

Here is the error message and my design.

=============================================

Error(14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. 

Error(175020): The Fitter cannot place logic pin that is part of gflish gflish in region (79, 120) to (79, 120), to which it is constrained, because there are no valid locations in the region for logic of this type. 

Info(14596): Information about the failing component(s): 

Info(175028): The pin name(s): clk_clk 

Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: 

Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected) 

Info(175029): B16 

Info(175015): The I/O pad clk_clk is constrained to the location PIN_B16 due to: User Location Constraints (PIN_B16) 

Info(14709): The constrained I/O pad is contained within this pin 

Error(175020): The Fitter cannot place logic pin that is part of gflish gflish in region (79, 129) to (79, 129), to which it is constrained, because there are no valid locations in the region for logic of this type. 

Info(14596): Information about the failing component(s): 

Info(175028): The pin name(s): reset_reset 

Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: 

Error(175005): Could not find a location with: IO_FUNCTION of GPIO (1 location affected) 

Info(175029): L14 

Info(175015): The I/O pad reset_reset is constrained to the location PIN_L14 due to: User Location Constraints (PIN_L14) 

Info(14709): The constrained I/O pad is contained within this pin 

[KhaiChein_Y_Intel]

Hi,

The error indicates that the specified logic was constrained to the specified region, but the Fitter cannot place the logic because there are no valid locations in this region for the specified logic. Coud you check the pin assignment for PIN_B16 and PIN_L14?

Thanks.

Best regards,

KhaiY

[scong4]

Thank you for you reply.

The attachment file is the full project , please check it.

[KhaiChein_Y_Intel]

Hi,

There is an error while extracting the file. Could you create the design.qar by clicking on Project > Archive Project?

Extracting ip\gflish\gflish_intel_generic_serial_flash_interface_top_0\intel_generic_serial_flash_interface_csr_180\synth\intel_generic_serial_flash_interface_csr.sv

Error: The system cannot find the path specified.

Cannot create C:\Users\khai\Desktop\open\gflish\ip\gflish\gflish_intel_generic_serial_flash_interface_top_0\intel_generic_serial_flash_interface_if_ctrl_180\synth\gflish_intel_generic_serial_flash_interface_top_0_intel_generic_serial_flash_interface_if_ctrl_180_rl2nqhy.sv

Irrecoverable Error: Extract operation failed.

Thanks.

Best regards,

KhaiY

[scong4]

OK,send to you the .qar file. rd02@njsunpower.com

[KhaiChein_Y_Intel]

Hi,

I could not see the attachment for the QAR file. Could you reattach?

Thanks.

Best regards,

KhaiY

[scong4]

Hi,

How about my question ?​

[scong4]

it seems something wrong , send to you again.​

[KhaiChein_Y_Intel]

Hi,

Upon checking, the error is caused by the incorrrect pin assignment. The I/O pin "clk_clk~CLUSTER" and "reset_reset~CLUSTER" are GPIO, but "B16" and "L14" has no GPIO resource.  Could you reassign both pins to another location?

For example, clk_clk to PIN_AK9, reset_reset to PIN_U7

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY

[scong4]

I set the clock to pin AL20 and reset to pin AK18 and passed the pin assignment , but this is not what I expect .

[KhaiChein_Y_Intel]

Hi,

Could you explain what is the expectation?

Thanks.

Best regards,

KhaiY

[scong4]

I have a board , it only use HPS_CLK and HPS_RESET, no other clock input , so I think I can use HPS_CLK and HPS_RESET to do same thing.

[KhaiChein_Y_Intel]

Hi,

The error occured is due to the incorrect pin assignment. Once you change the pin location of the two pins, the error is gone. May I know what is the expectation?

Thanks.

Best regards,

KhaiY

[scong4]

Can I use HPS Clock to generate a clock and use this clock to drive my design ?

[KhaiChein_Y_Intel]

Hi,

According to the User Guide, output clocks from HPS are not intended to be fed into PLLs in the FPGA. Therefore, you cannot use the HPS clock to generate a clock.

Source: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an763-a10-soc-device-design-guidelines.pdf

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY

[scong4]

NO , I worked on other projects for a while, will work on this project next week .If I have any problem , I 'll ask you.

[KhaiChein_Y_Intel]

Hi,

Do you still see the first error in the design after changing the pin location? If no, you may open a new forum thread to ask new question. This helps other customers to find the answer easily wihout having to read a complicated forum thread with multiple questions.

Best regards,

KhaiY

[scong4]

Yes ,I still see the first error . After I confirm this problem ,I'll colse this .

[KhaiChein_Y_Intel]

Hi,

Sure. Please keep me updated.

Thanks.

Best regards,

KhaiY