Agilex™ 5 EMIF IP for Hard Processor Subsystem (HPS) in Quartus 24.3.1

[Nicole04]

Good day,

I had a working EMIF IP set up and connected to the HPS in Quartus 24.2. I then upgraded to Quartus 24.3.1 and now can no longer get the EMIF IP to compile without errors. I replaced the old EMIF IP with the HPS EMIF IP (emif_io96b_hps). 

I can generate the HDL from Platform Designer without any errors. I get the following error when compiling:

Error(17821): Netlist error at hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4.vhd(275): port 's1_axi4_wuser' of width 64 cannot connect to actual of width 32

Details:

• Quartus 24.3.1 is used with all IP upgraded.
• I connect the io96b0_to_hps conduits of the HPS and HPS EMIF together. 
• The channel 1 axi4 wuser is 32 bits wide for both the HPS and EMIF:
  
  
• I am using LPDDR4 with configuration of 2x16 (8Gbit).
• In hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4.vhd the wuser signals are all of width 32.

I am unable to see where the 64-bit wide signal is and how to fix it.

C:/Firmware/CheetahTacticalRouter/tactical-router-fw/tactical_router_fpga/quartus/ip/hps_system/hps_system_emif_io96b/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy/synth/ip/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4/synth/hps_system_emif_io96b_emif_io96b_hps_200_7xwqmpy_emif_0_lpddr4.vhd

[sstrell]

Can you show your connections and parameter settings in PD?

[Nicole04]

Good day,

Platform Designer Connections:

EMIF Parameters:

HPS Parameters:

I added the last two images for the HPS Parameters as attachments, because they did not want to load here.

The system compiled without errors in Quartus 24.2. I had to upgrade the HPS and EMIF IP, the remaining HPS related IP did not change.

Let me know if you require any further information.

[sstrell]

It looks OK.  Is this an example design you generated or a design you built yourself?  Perhaps try generating the example design and then customize that as needed if you built this manually.

[Nicole04]

Good day,

This is not an example design; no example design exists for this. The Quartus 24.2 design was based on the development kit and worked. This seems to be either an issue with the latest Quartus (24.3.1) or the updated IP Cores for this version.

If I remove the EMIF then it complains about other HPS pins, such as USB2 not being connected, however it is not something that is done outside of the IP core and the settings show it is connected. This is why I think there may be issues with the HPS IP.

[sstrell]

No, I mean a customized example design you generate from the IP Parameter Editor that creates a whole project for you based on the settings you specify in the Parameter Editor.  This is a good way to create a complete design quickly.

[Nicole04]

Yes, I understand, but there is no option for this.

Is there a different path from which this can be done?

[sstrell]

Your screenshot is for your PD system, not the IP itself.  You have to go into the IP parameter editor for the EMIF and there is an Example Design tab for configuring the example design and a button in the upper right to generate the example design based on the parameter settings.

https://www.intel.com/content/www/us/en/docs/programmable/817394/24-3-1/about-the-external-memory-interfaces-fpga-ip.html

[Nicole04]

This is the error I get when trying to generate the example design. It is not available.

Has the updated IP been tested?

[Nicole04]

I realized that the error disappears when the EMIF (in HPS and EMIF IP parameter settings) is set to 1x32 instead of 2x16.

[Jeet14]

Hi,

Thanks Sstrell for helping on customer issue.

Looks like this issue is resolved now.

Regards

Tiwari

[Nicole04]

Hi Tiwari,

The issue has not been resolved. I need to use the 2x16 architecture. 

The 1x32 also stopped working after regenerating the HDL. I get the following error for it too:
Error(17821): Netlist error at emif_bank2a_fpga.vhd(175): port 's0_axi4_wuser' of width 64 cannot connect to actual of width 32

The s0_axi4_wuser port is of width 32 in the mentioned .vhd file. 

Please assist with this issue. 

Kind regards,

Nicole

[mfiorenza]

Any resolution to this issue? I am also running into this issue on 24.3.1. However, for me it is with the EMIF IP (Not for HPS) variant. The EMIF for HPS worked fine for me, however, I am using it as 1x32. The EMIF IP for FPGA DDR is also configured the same 1x32 but I am running into the issue above.

Both DDR (HPS and FPGA) are identical. Both configured as 1x32 for LPDDR4. HPS EMIF IP compiles fine, EMIF IP for FPGA DDR fails to compile with the same error mentioned above. I try to inspect the source where the error is originating however it appears to be two 32-bit wide ports connecting so I'm not sure where the 64-bit is coming from.

I also never had any issues with prior versions of Quartus. Please advise. 

[Nicole04]

Unfortunately, I have not received any feedback from Intel regarding this issue. 

If I find a work-around I will be sure to let you know.

[AdzimZM_Intel]

Hi Nicole,

I cannot replicate the issue at my end. Can you share a small design that replicate this issue?

I can see a warning message that may sound related, but no error messages reported.

Warning(24541): Verilog HDL warning at as_emif_io96b_hps_0_emif_io96b_hps_200_e2lhgoi_emif_0_lpddr4.v(230): actual bit length 32 differs from formal bit length 64 for port "s1_axi4_ruser" 

Regards,

Adzim

[Nicole04]

Hi Adzim,

Due to confidentiality, I can unfortunately not share my current design, but I had a similar issue (with 1x32) with a development kit. Here are those files. The full project is too large to share (let me know if I can email it). I have attached the top level and hps .qsys files.

We make use of VHDL. The warning you get is definitely related to the error that I get. 

Kind regards,

Nicole

[AdzimZM_Intel]

Hi Nicole,

Thank you for your feedback.

I will try to replicate the issue again with the file that you have shared.

Regards,

Adzim

[mfiorenza]

I have attached my project below for reference if it will help. My project only has the Agilex5 HPS IP, HPS EMIF IP, and FPGA EMIF IP. Both LPDDR4s are the same. HPS EMIF IP compiles successfully but the FPGA EMIF IP leaves me with the error (s0_axi4_wuser) shown above.

[MM-ATH]

We had similar problems  - if we have checked Compile to VHDL (in Platform Designer/generate HDL). if ve have checked Compile to Verilog, problem gone away.

[AdzimZM_Intel]

Hi,

The issue can be replicated if the EMIF IP is used VHDL code.

There is a parameter where the axi4_wuser width is determined.

If it does not use the NoC, the width is set to 64 for axi4_wuser.

The parameter can be found in the EMIF IP file path *_emif_io96b_lpddr4_0\emif_io96b_lpddr4_200\synth\*_emif_io96b_lpddr4_0_emif_io96b_lpddr4_200_*.sv.

localparam PORT_AXI_USER_WIDTH   = 64,

localparam PORT_AXI_NOC_USER_WIDTH = 32,

localparam PORT_AXI_S0_USER_WIDTH  = PHY_USE_NOC_INTF ? PORT_AXI_NOC_USER_WIDTH : PORT_AXI_USER_WIDTH,

Change the PORT_AXI_USER_WIDTH = 64 to 32 can resolve this error message.

Can you try to change the port width to 32 and check the compilation again?

Regards,

Adzim

[MM-ATH]

Thanks Adzim,

Yes, this change leads to good compilation on our testing design.