Disable Quartus timing analyzer inverted clock

[AEsqu]

Hello,

Is there a way to disable the inverted clock latch analysis in quartus 20.1 for arria 10?

I had no such inverted clock analysis with the same design using Quartus 13.1 on stratix 3

, with similar sdc constraints (and design was running fine on board).

Timings are very bad with this inverted clk analysis (gated clock on falling edge).

[sstrell]

Can you post your SDC?  This is pretty strange.  It also looks like all the failures are on paths that are fanning in to a single clock enable input which seems odd.  Can you post any of the HDL for this part of the design?

#iwork4intel

[AEsqu]

I cannot share RTL code.

I use this kind of constraints for now to remove those timing checks:

set_false_path -fall_to [get_clocks {mcu_clk}] -from [get_registers {*|u_rfd_clockshop|i_apb_if|s_sw_all_periph_reset_en}]

set_false_path -rise_from [get_clocks {mcu_clk}] -to [get_registers {*|u_flash_subsys|A_ip_pflash640k_atfc|u_controller|u_fmc_if|start_gate|u_cgate|ClkEnable*}]

[AEsqu]

Here is the SDC.

For this run, variables are set to:

$is_a_quartus_only_project == "0"

$current_project == "Achilles_arria_X"

$is_a_quartus_project == "1"

[KennyTan_Altera]

You need to look into your rtl viewer whether the launch and latch clock make sense. set false path will remove the analysis but it might cause functional failure if those path are valid analysis.

If you can provide us a rtl screenshot on those path will be good.

[AEsqu]

Quartus 20.1/arria 10 had too hard time to analyze the design with the test logic (test mode can then be enabled or not based on an input pin).

There was no issue with Quartus 13.1/stratix 3 FPGA.

I have the impression that Quartus 20.1 checks much more timings than Quartus 13.1 was (expecially those inverted checks).

At the moment I disabled/removed the test logic to ease quartus place and route.

[KennyTan_Altera]

yes, there should have a lot improvement done compare to the old quartus. You will have to analyze whether this make sense from your side. Or you can send us your design to have a look.

[KennyTan_Altera]

any update?

[AEsqu]

My colleague mentioned to me that he's not surprised that there are much more hold timing violations for smaller device node (arria 10 vs stratix 3).

Can you confirm that it is more difficult to achieve positive hold slack on arria 10 devices compare to stratix 3 for example?

[KennyTan_Altera]

We can't confirm on this. As we do not do benchmark for old device e.g. Stratix III.

What you can do is open up the timing analyzer to do the comparison. It should show you all the details there.

I would suggest you attend the timing closure class as well. Look into the prerequisite before attending the timing closure class, as you might need to know on timing analyzer as well.

https://www.intel.com/content/www/us/en/programmable/support/training/course/odswtc02.html

Thanks

[AEsqu]

Finally got it timing clean (fixes hold time violation on arria 10 with quartus 20.2) using other settings,

see attached file.

[AEsqu]

And the qsf settings according it.

[AEsqu]

Unfortunately the bad hold timing violation plague is back using a new netlist of synplify pro.

I don't know what quartus is doing anymore.

Why is it adding +12 ns mlab routing all around the fpga ...

[KennyTan_Altera]

Can you attached your design.qar files to have a look?

Let us know if you want to send it to us privately.

[KennyTan_Altera]

Any update for the previous request?

[KennyTan_Altera]

We do not receive any response from you to the previous reply that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 

[AEsqu]

Hi,

I cannot provide a test case, sorry.