Programmable Devices

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Programmable Devices

Discussions

lpm_add_sub - signed

Cyclone V Transceiver Synchronised 32bit Word Alignment Problem

synthesizing altera design, with altera megafunction, using synplify

DDR3 memory chips for Arria V GX devices (5AGXMB1G6)

Symbol generation in Quartus 16

Altera FPGA Security solution? How to choose main chip?

Can not download package of cycloneiv

stratix IV GX70 1152 pin altlvds_rx+altpll problem

With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?

About unused pins of CycloneIV

DDR3 memory controller endianess

Cyclone III not configuring, using AS.

msel in multiple configuration schemes

MAX7000 max output current question

DE1-SoC IP problem

Featured Content

AGILEX5 - HPS-first - timeout waiting for RECONFIG_COMPLETED

10M04SCU324I7G - I/O timing

SDI pinning on Agilex 5

I350 igb driver failed with error -2

Request for the Product Lifecycle Status

Re: USB Blaster selection criteria

Solution: USB Blaster Driver for Windows 11 ARM