Programmable Devices

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Programmable Devices

Discussions

Is it possible to configure the EPCS device through FPGA via JTAG only?

Arria 10 GX 1150 Registers

Max10 fpga adc

Cyclone V SOC - SOCKit - all HSMC pins are high during FPGA config loading

Downloading software to the CPLD chip from another processor

Cyclone lll LVDS IO

I cannot generate .sof file

PLL Phase shifting with reconfig controller

launch signal tap thru command line

Programmer file not update after I recompile the VHDL file

IP Catalog won't display/open

Getting Actual Support From Altera

I cannot receive a pattern if there are many consecutive '1's without encoding it

PowerPlay Early power Estimator(EPE) for Arria10 device

Unused bank - VCCPD, VCCIO and VREF pins

Featured Content

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

EPM3064ATC44-7N and EPM3064ATI44-10N

Quartus Prime Design Software - JTAG usage

Re: Download speed

Re: Quartus Prime Design Software - JTAG usage