Programmable Devices

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Programmable Devices

Discussions

QDRII+ IP core error

Generating a signal with noise

Configuration pins vs. registers of PHY 88E1111

Problem opening .qar archive

Does Cyclone4 support DDR2 DIMM?

Using PFL megafunction to configure 7 stratix V FPGAs using two 2Gb CFI Flash

VHDL Model & Synthesis of Traffic Light Controller

NIOS II self test

Error when porting from SOPC Builder to QSys

Quartus II simulator

monitoring all the pins

How to implement an histogram in a FPGA device??

How to pin list..?

Stratix Hardware design

FPGA fried?

Featured Content

Quartus Prime Design Software - JTAG usage

p0_pin_perst_n remains asserted when implementing GTS AXI Streaming intel FPGA IP for PCI Express

EPM3064ATC44-7N and EPM3064ATI44-10N

Re: Download speed

Re: Quartus Prime Design Software - JTAG usage