FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

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differences between intel item and ENPIRI( and ALTERA)

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rx control signal of enhanced standard pcs of transceiver

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Problem with Fitter LL Ethernet 10G R core rx/tx_serial I/O

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Access Configuration Flash pins via Deneric Serial Flash IP- can't assign them via Pin Planner

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Avalon MM Slave - What's the simple way to extract the above lines from QSYS to HDL?

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How to receive lvds DDR data

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Stratix 10 Mailbox Client IP: max input clock frequency specification

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mSGDMA mm_Read Data is slow, but mm_Write Data is fast (ok) for "TSE_mSGDMA to HIP AVMM-DMA" logic

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714

Where download “IP_ORAN_FH” linux “oran-21.2.xxx-linux.run” installer package ?

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899

Cyclone v native transceiver IP -data corrupted issue

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Help with Cyclone V Transceiver Native PHY IP Core

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ALTERA_FP_MATRIX_INV in Floating-point IP core

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Coefficient reload problem of FIR IP core

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Intel license IP - PECI

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1546

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EMIF - ref_clk from a bank other than address control and share that ref clock for 2 EMIF instances

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how to expand the pcie rx completion buffer size?

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Stratix10 PHYLite: avl_readdata on Avalon Interface Always Returning 0

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FPGA Intellectual Property

Discussions

differences between intel item and ENPIRI( and ALTERA)

O-RAN Intel FPGA IP Example

rx control signal of enhanced standard pcs of transceiver

Problem with Fitter LL Ethernet 10G R core rx/tx_serial I/O

Access Configuration Flash pins via Deneric Serial Flash IP- can't assign them via Pin Planner

Avalon MM Slave - What's the simple way to extract the above lines from QSYS to HDL?

How to receive lvds DDR data

Stratix 10 Mailbox Client IP: max input clock frequency specification

mSGDMA mm_Read Data is slow, but mm_Write Data is fast (ok) for "TSE_mSGDMA to HIP AVMM-DMA" logic

Where download “IP_ORAN_FH” linux “oran-21.2.xxx-linux.run” installer package ?

Cyclone v native transceiver IP -data corrupted issue

Help with Cyclone V Transceiver Native PHY IP Core

ALTERA_FP_MATRIX_INV in Floating-point IP core

Coefficient reload problem of FIR IP core

Intel license IP - PECI

Featured Content

EMIF - ref_clk from a bank other than address control and share that ref clock for 2 EMIF instances

how to expand the pcie rx completion buffer size?

Stratix10 PHYLite: avl_readdata on Avalon Interface Always Returning 0