Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Discussions

Post a question

Stratix II EP2S90F1020 JTAG issue

by on Latest post on by

3 Replies 1057 Views

1057

no source code in the intel example project of [Arria10 FPGA RSU via PCIE ]

by on Latest post on by

5 Replies 1905 Views

1905

Flash size selection for the S10TX2800 device configuration

by on Latest post on by

5 Replies 1730 Views

1730

Transciever debug script

by on Latest post on by

2 Replies 1180 Views

1180

MAX10 CFM most significant bit read addresses being cut off

by on Latest post on by

2 Replies 1383 Views

1383

Arria 10 Transceiver Receiving Flipped/Reversed Data

by on Latest post on by

5 Replies 2606 Views

2606

Cyclone VE DDR3 SDRAM controller generation issue

by on

0 Replies 511 Views

511

Is it not possible to use all clock outputs of an Arria 10 IOPLL

by on Latest post on by

23 Replies 6158 Views

6158

How to create SPI slave in FPGA when SCLK frequency is of order comparable to FPGA system clock?

by on Latest post on by

6 Replies 2533 Views

2533

Cyclone III programming problem (JTAG and AS)

by on Latest post on by

30 Replies 11077 Views

11077

Hyper Bus implementation on MAX-10 FPGA

by on Latest post on by

1 Reply 587 Views

587

I/O Standard

by on Latest post on by

8 Replies 1987 Views

1987

MAX10DAF vs MAX10DCF Compatibility if not using the ADC

by on Latest post on by

2 Replies 825 Views

825

Who has the reference design of alt2gxb IP, in source code form

by on Latest post on by

1 Reply 483 Views

483

Arria 10 Fitter Error - "Cannot find a legal configuration for the following atoms"

by on Latest post on by

1 Reply 1154 Views

1154

Popular Discussions

Issue with Pixel Buffer DMA AVMM -> AXI connection on DE25-Standard (Agilex5)

0 7

Deserializers in Agilex 3 series

0 7

Top kudoed authors

Epsum factorial non deposit quid pro quo hic escorol.

User

Count

Re: Download speed

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.

Programmable Devices

Discussions

Stratix II EP2S90F1020 JTAG issue

no source code in the intel example project of [Arria10 FPGA RSU via PCIE ]

Flash size selection for the S10TX2800 device configuration

Transciever debug script

MAX10 CFM most significant bit read addresses being cut off

Arria 10 Transceiver Receiving Flipped/Reversed Data

Cyclone VE DDR3 SDRAM controller generation issue

Is it not possible to use all clock outputs of an Arria 10 IOPLL

How to create SPI slave in FPGA when SCLK frequency is of order comparable to FPGA system clock?

Cyclone III programming problem (JTAG and AS)

Hyper Bus implementation on MAX-10 FPGA

I/O Standard

MAX10DAF vs MAX10DCF Compatibility if not using the ADC

Who has the reference design of alt2gxb IP, in source code form

Arria 10 Fitter Error - "Cannot find a legal configuration for the following atoms"

Featured Content

Agilex 3 GTS PCIe IP missing

Issue with Pixel Buffer DMA AVMM -> AXI connection on DE25-Standard (Agilex5)

Deserializers in Agilex 3 series

Re: Download speed