Programmable Devices

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Programmable Devices

Discussions

Cyclone IV IBIS Model

MAX 10 FPGA power-on/configuration error

FPGA with DDR5 or HBM2 memory

Cyclone V PLL : "Normal" mode compensation is not working.

interfacing to epcq256 through fpga

MAX 10, using LVDS differential clock input.

Interfacing to epcs64 from fpga

Landing pattern for BGAs: IPC vs. Altera recommendation?

How to solve modelsim simulation fir compiler Library auk_dspip_lib not found?

Timing Simulation error in Quartus prime 16.1

ARM Training

How to Calculate Pixel Buffer Size for Varying Kernel Sizes

DE4_230 (Stratix GX IV) Terasic FAN CONFIGURATION PROBLEM

How to Parse a JPEG file instead of PPM

FPGA Development Board - strange shift operation behavior

Featured Content

Agilex 3 GTS PCIe IP missing

Quartus 25.1.1 Pro Fitter Error with Agilex3

Issue with Pixel Buffer DMA AVMM -> AXI connection on DE25-Standard (Agilex5)

Re: LVDS pin detail on Arria 10

Re: Download speed