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All support for Intel NUC 7 - 13 systems has transitioned to ASUS. Read latest update.



Transceiver Design Flow

Transceiver IBIS-AMI Models 

  1. High-Speed Serial Link Analysis with IBIS-AMI Models

Stratix V Hard IP for PCI Express

1.      IP for PCI Stratix V Hard IP for PCI Express User Guide

2.      Stratix V Hard IP For PCI Express Instantiation Walkthrough

3.      Simpler Chaining DMA Testbench Guide

Stratix V 10GBASE-R PHY IP Design Example

1.      10GBase-R Design Example

Stratix V 10GBASE-KR PHY IP Design Example

1.      10GBase-KR Design Example 

Stratix V PCI Express (PIPE) Design Example

1.      PIPE Design Example

Stratix V Interlaken Design Example

1.      Interlaken Design Example

Stratix V XAUI PHY IP Design Example

1.      XAUI Design Example

Stratix V GIGE Design Example

1.      GIGE Design Example

Stratix V PMA Controls Reconfiguration Design Example

1.      PMA Controls Reconfiguration Design Example

Stratix V Custom PHY IP with PMA Controls Reconfiguration Design Example

1.      Custom PHY IP with PMA Controls Reconfiguration Design Example

Transceiver Toolkit Designs (Unofficial)

1.      Transceiver Toolkit

High-Speed Demo Designs for Current and Older Families (100+ designs in total)

1.      High-Speed Transceiver Demo Designs

Simulate Arria V Native PHY IP Rate Match FIFO underclock compensation condition

1.      Simulate_Arria_V_Native_PHY_IP_Rate_Match_FIFO_under_clock_compensation_condition

Arria 10 Transceiver PHY Design examples

1.      Arria_10_Transceiver_PHY_Design_Examples


Transceivers, Transceiver Toolkit, Verilog Code Snippets, Stratix V design examples, Arria 10 design



Version history
Last update:
‎07-06-2021 03:02 PM
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