FPGA Intellectual Property

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.

FPGA Intellectual Property

Discussions

(need help)3X3 Hardware Matrix Multiplier as QSYS custom component

Help with DDR2 SDRAM DIMM with UniPHY on Stratix III eval board

test pattern generator (VIP)

Reed Solomon IPcore 13.0 problem

Altera Compact flash IP Core Performance

Serial RapidIO Mesh Network?

DDR2 half-rate works, not full-rate

Output Latency for Integer Arithmetic Megacore at Cyclon Family

sopc_buider_IP Core

Using Serial RapidIO?

Problems with UniPHY IP not accepting commands on Cadence

UDP Offload example

Need help with DE2 Audio Codec

Stratix V PCIE hardcore not detected in bios with Intel chipset C600

XAUI core simulation for Cyclone V

Featured Content

Error: (vsim-3033), Error Loading Design

EPCQ16ASI8N marking

[Case:764094]Technical Data Inquiry for Elettronica S.p.A.

Re: Re:How to switch the HDMI PHY reference clock to the HDMI Rx TMDS clock ?

EPCQ16ASI8N marking